le79128 Zarlink Semiconductor, le79128 Datasheet - Page 14

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

TRANSPORT LAYER
The primary responsibility of the transport layer is to move 16-bit data words between the physical interface and the device’s
internal memory. Data is organized into transport frames, which consist of a 16-bit command word followed by 0 or more data
words. The command word provides address and length information to the transport hardware. In a sense, this hardware provides
an internal DMA-like function, moving data over the internal bus under host control. Both the GPI and SPI physical layers share
a common transport layer.
Interface Addressing
The transport command word provides address information to the interface hardware.
The host interface address model is based on a paged memory scheme as shown in
to 257 pages, with up to 128 offset-addressable 16-bit wide register locations. Therefore, an interface address is composed of an
8-bit page number and a 7-bit register offset. Pages are selected by using a command to write the page register. All data access
commands operate on the selected page. One exception is the direct page, which can be accessed at any time without changing
the page register.
Address
Offset
127
0
Figure 4. Host Bus Interface Address Model
120 - 127 Reserved
Direct Page
Page 0
Registers
16-Bit
Page 1 ... N
Microsemi Corporation - CMPG
Page 255
Le79128
14
Notes:
1. Page 255 is reserved for loading code.
2. N = 15.
Figure
4. The command design permits up
Preliminary Data Sheet