le79128 Zarlink Semiconductor, le79128 Datasheet - Page 33

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

Note:
1.
2.
3.
4.
Refer to Figure 26 for timing diagram test points.
The Wait Strobe active edge may occur as early as the rising Write Strobe signal if Chip Select is held active.
The pin load is assumed to be C
This is the time between the read command and the first data word. If PWAIT is not used, then the maximum value must be met by the host.
If PWAIT is used, faster transactions can occur.
PCS
PDS
PADDR
PD[7:0]
PRD/WR
Table 16. GPI Bus Timing Parameters for Combined Read/Write and Data Strobes
No.
10
11
1
2
3
4
5
6
7
8
9
Note: Each Write and Read access is qualified by an active chip select strobe. (Chip select can be tied Low in some applications.)
t
HOLD_OUT
t
t
Symbol
t
t
WR_RDV
HOLD_IN
CS_WAIT
WAIT_DV
Figure 11. GPI 8-Bit Write Access Using Combined Read/Write and Data Strobes
t
CMD1_1
t
RD_DV
t
SU_IN
t
t
WAIT
t
2
ACC
OFF
ON
1
Access period (from Write to Write or Read to
Read or Read to Write)
Pulse width LOW (PCS or PRD/WR or PDS)
Pulse width HIGH (PCS & PRD/WR & PDS or
PCS & PDS)
Write to Read (rising PRD/WR to Data output
valid)
PCS, PADDR, PRD/WR active to Data output
valid
Address, Data input setup time to rising PCS or
PRD/WR or PDS
Address, Data input hold time after rising PRD/
WR or PDS or PCS
Data output hold time after rising PDS or PCS
Chip Select active to Wait active
Wait strobe active width when PCS is active
PWAIT deserted to Data valid
load
3
6
= 75pF.
7
CMD1_2
Parameter
Microsemi Corporation - CMPG
Le79128
33
DATA1_1
Min
100
35
10
25
15
—
—
—
0
0
0
DATA1_2
Typ
80
—
—
—
—
—
—
—
—
—
—
Preliminary Data Sheet
1
Max
270
280
—
—
—
25
—
—
10
25
0
Unit
ns
Note
3,4
2,3
2,3
3
3
2