le79128 Zarlink Semiconductor, le79128 Datasheet - Page 16

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

Select Page
This command selects the active interface page. It is a write only command and is followed by 0 data words. The 8-bit page field
allows up to 256 selectable pages to be defined.
Configure Interface
This command is used to configure various physical interface options. It is a write-only command and is followed by 0 data words.
The Interface Option Bits field allows the following features to be programmed by the host: Wait Pin Polarity (active High or active
Low), Wait Pin Enable (default is tri-state), Wait Pin Drive Mode (open-source/open-drain or TTL), Interrupt Pin Drive Mode (open-
drain or TTL), and Endian Control (Big or Little). If this register is not programmed correctly, it is possible that the host may not
be able to communicate with the VCP device properly. This should be part of the HAL (Hardware Abstraction Layer) function used
to initialize the device.
Note:
The commands are not affected by endianness; their order must be maintained per documentation. Hence, little-endian systems will need to re-
verse the command structure.
NOP
A command is reserved to serve as a NOP. Note that all commands except for the Offset Access commands are implemented by
reserving an address from the direct page.
HBI Page Selection (PGSEL)
PG_SEL:
HBI User Interface Pin Configuration (PINCONFIG)
RSVD:
INT_DRV:
PWAIT_DRV:
PWAIT_EN:
PWAIT_POL:
END_SEL:
RSVD
D7
D7
RSVD
D6
D6
Page addressed by any non-direct HBI access.
Should be written as 0.
INT pin drive mode.
0: Open drain (default).
1: TTL.
PWAIT pin drive mode.
0: CMOS-drive (default). Pin is actively driven to both polarities. When PCS is
1: Open source or drain depending on polarity. Pin is actively driven to its active
PWAIT pin enable.
0: Disabled (default).
1: Enabled.
PWAIT pin polarity.
0: Active Low (default).
1: Active High.
Endian select.
0: Big endian (default).
1: Little endian.
deasserted (High), the PWAIT pin is driven inactive.
polarity as specified by the PWAIT_POL setting. When PCS is deas-
serted(High), the PWAIT pin is tri-stated.
RSVD
Microsemi Corporation - CMPG
D5
D5
Le79128
INT_DRV
16
D4
D4
PG_SEL [7:0]
PWAIT_DRV
D3
D3
PWAIT_EN
D2
D2
Preliminary Data Sheet
PWAIT_POL
Command 0xFD (W)
Command 0xFE (W)
D1
D1
END_SEL
D0
D0