ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 99

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
5.1.42 INTSTS (030h) (Master Mode)
INTerrupt STatuS Register. The Interrupt status register contains the interrupt request status of
each of the three timers, Timer2, Timer1, and Timer0 (see Table 63).
Table 63. Interrupt Status Register (Master Mode)
5.1.43 INTSTS (030h) (Slave Mode)
When NMIs occur, the interrupt status register controls DMA operation and the interrupt request
status of each of the three timers, Timer2, Timer1, and Timer0 (see Table 64).
Table 64. Interrupt Status Register (Slave Mode)
15
DHLT
15
DHLT
Note: The TMR bit in the REQST register is a logical OR of these timer
interrupt requests.
Bits [15–4]—Reserved. Set to 0.
Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK
bit is 0. The interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt
Mask Register has a duplicate of this bit.
Bits [2–0]—PR [2–0] Priority → These bits define the priority of the serial port interrupts
in relation to other interrupt signals. The interrupt priority is the lowest at 7 upon reset.
The values of PR2–PR0 are shown above.
Bit [15]—DHLT DMA Halt → DMA activity is halted when this bit is 1. It is set to 1
automatically when any non-maskable interrupt occurs and is cleared to 0 when an IRET
instruction is executed. Interrupt handlers and other time-critical software may modify
this bit directly to disable DMA transfers. However, the DHLT bit should not be
modified by software if the timer interrupts are enabled as the function of this register as
an interrupt request register for the timers would be compromised.
Bits [14–3]—Reserved.
Bits [2–0]—TMR [2–0] Timer Interrupt Request → When any of these bits is 1,
a pending interrupt request is indicated by the respective timer.
14
14
13
13
12
12
®
11
11
Reserved
Reserved
10
10
9
9
8
8
UNCONTROLLED WHEN PRINTED OR COPIED
7
7
6
6
Page 99 of 154
IA211050902-15
5
5
4
4
3
3
2
TMR2–TMR0
2
TMR2–TMR0
1
1
0
0
December 24, 2008
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