ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 42

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n
2.2.40 s6/lock_n/clkdiv2_n/pio29—Bus Cycle Status Bit [6] (synchronous output)/Bus
The s6 signal is high during the second and remaining cycle periods (i.e., t
DMA-initiated bus cycle is under way. The s6 is tristated during bus hold or reset.
The lock_n signal is held low to indicate to other system bus masters that the system bus is being
used and that no attempt should be made to try to gain control of it. This signal is only available
during t
The microcontroller enters clock divide-by-2 mode, if clkdiv2_n is held low during power-on-
reset. In this mode, the PLL is disabled and the processor receives the external clock divided
by 2. Sampling of this pin occurs on the rising edge of res_n.
Should this pin be used as pio29 configured as an input, care should be taken that it is not driven
low during power-on-reset. This pin has an internal pullup so it is not necessary to drive the pin
high even though it defaults to an input PIO.
2.2.41 srdy/pio6—Synchronous Ready (synchronous level-sensitive input)
This signal is an active high input synchronized to clkouta and indicates to the microcontroller
that a data transfer will be completed by the addressed memory space or I/O device.
In contrast to the asynchronous ready (ardy), which requires internal synchronization, srdy
permits easier system timing as it already synchronized. Tying srdy high will always assert this
ready condition, whereas tying it low will give control to ardy.
2.2.42 tmrin0/pio11—Timer Input 0 (synchronous edge-sensitive input)
This signal may be either a clock or control signal for the internal timer 0. The timer is
incremented by the microcontroller after it synchronizes a rising edge of tmrin0. When not used,
tmrin0 must be tied high, or when used as pio11 it is pulled up internally.
s2_n
0
0
0
0
1
1
1
1
1
s1_n
Lock (synchronous output)/Clock Divide by 2 (input with internal pullup)
and is intended for emulator use.
0
0
1
1
0
0
1
1
s0_n
0
1
0
1
0
1
0
1
®
Interrupt acknowledge
Read data from I/O
Write data to I/O
Halt
Instruction fetch
Read data from memory
Write data to memory
None (passive)
Bus Cycle
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IA211050902-15
2
–t
4
), indicating that a
December 24, 2008
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