ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 36

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
2.2.19 int2/inta0_n/pwd/pio31—Maskable Interrupt Request 2 (asynchronous
The int2 pin provides an indication that an interrupt request has occurred. Provided that int1 is
not masked, program execution will continue at the location specified by the int1 vector in the
interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled. When int0 is configured to be in
cascade mode, int2 changes its function to inta0_n.
The inta0_n function indicates to the system that the microcontroller requires an interrupt type in
response to the interrupt request int0 when the microcontroller’s Interrupt Control Unit is in
cascade mode.
The pwd processes a signal via the Schmitt trigger when pulse width demodulation is enabled. It
drives timrin0 and int2 and its inverse signal drives timrin1 and int4. Provided that int2 and int4
are enabled and timer0 and timer1 are configured correctly, the pulse width of the alternating
signal on pwd may be calculated from the values in timer0 and timer1.
While in pwd mode, tmrin0/pio11, tmrin1/pio0, and int4/pio31 signals are free for use as PIOs or
may be ignored. The level on this pin is held in the PIO data register in the pio31 position, just
as if it were a PIO.
2.2.20 int3/inta1_n/irq—Maskable Interrupt Request 3 (asynchronous input)/Interrupt
The int3 pin provides an indication that an interrupt request has occurred. Provided that int3 is
not masked, program execution will continue at the location specified by the int3 vector in the
interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled. When int1 is configured to be in
cascade mode, int3 changes its function to inta1_n.
The inta1_n function indicates to the system that the microcontroller requires an interrupt type in
response to the interrupt request int1 when the microcontroller’s Interrupt Control Unit is in
cascade mode.
With the Interrupt Control Unit of the microcontroller in slave mode, the signal on the irq pin
allows the microcontroller to output an interrupt request to the external master interrupt
controller.
input)/Interrupt Acknowledge 0 (synchronous output)/Pulse Width Demodulator
(Schmitt trigger input)
Acknowledge 1 (synchronous output)/Interrupt Acknowledge (synchronous
output)
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IA211050902-15
December 24, 2008
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