ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 53

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
4.14
There are six peripheral chip selects, pcs6_n, pcs5_n, and pcs3_n–pcs0_n, which may be used
within a user-defined memory or I/O block. Except for the spaces associated with the ucs_n,
lcs_n, and mcs_n chip selects, the base address can be located anywhere within the 1-Mbyte
memory-address space or programmed to the 64-Kbyte I/O space. The pcs4_n is not available.
None of the pcs_n pins are active at reset. The pcs6_n–pcs5_n and pcs3_n–pcs0_n may be
programmed to have 0 to 3 wait states. The pcs3_n–pcs0_n may be also programmed to have
5, 7, 9, and 15 wait states.
The PCS may be configured for 8- or 16-bit accesses by the AUXCON register. The PCS range
bus width is determined either by that of the non-UCS/non-LCS memory range or by the width
of the I/O space. The assertion of the PCS outputs occurs with the same timing as the
multiplexed AD address bus. Each of the PCS operates over a 256-byte address range.
4.15
The Refresh Control Unit (RCU) automatically generates refresh bus cycles with a fixed wait-
state value of three for the PSRAM automatic refresh mode. The RCU generates a memory-read
request after a programmable period of time to the bus interface unit.
The ENA bit in the Enable RCU register (EDRAM) enables refresh cycles, operating off the
processor internal clock. If the processor is in power-save mode, the RCU must be reconfigured
for the new clock rate.
If the hlda pin is asserted when a refresh request is initiated (indicating a bus-hold condition), the
processor disables the hlda pin to allow a refresh cycle to be performed. The external circuit bus
master must deassert the hold signal for at least one clock period to permit the execution of the
refresh cycle.
4.16
Interrupt requests originate from a variety of internal and external sources that are arranged in
priority order by the internal interrupt controller and are presented sequentially to the processor.
Eight external-interrupt sources are connected to the processor. These include seven maskable
and one nonmaskable interrupt (NMI). Eight internal-interrupt sources are also connected to the
processor. These include those not brought out to external pins—three timers, two DMA
channels, two asynchronous serial ports, and the WDT NMI. Interrupts int6 and int5
(multiplexed with drq1 and drq0) are available if the respective DMA is not enabled or is
internally synchronized.
Peripheral Chip Selects
Refresh Control
Interrupt Control
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Page 53 of 154
IA211050902-15
December 24, 2008
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