uc1682 ETC-unknow, uc1682 Datasheet - Page 44

• Manufacturer Part Number: uc1682
• Description: 80 X 104rgb C-stn Lcd Controller-driver W/ 32-shade Per Dot, 12-bit Per Rgb
• Manufacturer: ETC-unknow

U
High-Voltage Mixed-Signal IC
D
D
The input display data (depend on color mode)
are stored to a dual port static RAM (RAM, for
Display Data RAM) organized as 80x104X12.
After setting CA and RA, the subsequent data
write cycles will store the data for the specified
pixel to the proper memory location.
Please refer to the map in the following page
between the relation of COM, SEG, SRAM, and
various memory control registers.
D
The Display RAM is a special purpose dual port
RAM which allows asynchronous access to both
its column and row data. Thus, RAM can be
independently accessed both for Host Interface
and for display operations.
D
A Host Interface (HI) memory access operation
starts with specifying Row Address (RA) and
Column Address (CA) by issuing Set Row
Address and Set Column Address commands.
If wrap-around (WA, AC[0]) is OFF (0), CA will
stop incrementing after reaching the end of row
(103), and system programmers need to set the
values of RA and CA explicitly.
If WA is ON (1), when CA reaches the end of a
row, CA will be reset to 0 and RA will increment
or decrement, depending on the setting of row
Increment Direction (RID, AC[2]). When RA
reaches the boundary of RAM (i.e. RA = 0 or 79),
RA will be wrapped around to the other end of
RAM and continue.
MX I
Column Mirroring (MX) is implemented by
selecting either (CA) or (103–CA) as the RAM
column address. Changing MX affects the data
written to the RAM.
Since MX has no effect on the data already
stored in RAM, changing MX does not have
immediate effect on the displayed pattern. To
refresh the display, refresh the data stored in
RAM after setting MX.
R
COM electrode scanning orders are not affected
by Start Line (SL), Fixed Line (FL) or Mirror Y
(MY, LC[3]). Visually, register SL having a non-
42
ATA
ISPLAY
ISPLAY
OW
ISPLAY
LTRA
MPLEMENTATION
M
O
APPING
RGANIZATION
D
D
C
ATA
ATA
D
HIP
ATA
RAM A
RAM A
RAM
CCESS
DDRESSING
zero value is equivalent to scrolling the LCD
display up or down (depends on MY) by SL rows.
RAM A
The mapping of the data stored in the display
SRAM and the scanning COM electrodes can be
obtained by combining the fixed COM scanning
sequence and the following RAM address
generation formula.
When FL=0, during the display operation, the
RAM line address generation can be
mathematically represented as following:
Where Mod is the modular operator, and Line is
the bit slice line address of RAM to be outputted
to SEG drivers. Line 0 corresponds to the first bit-
slice of data in RAM.
The above Line generation formula produces the
“loop around” effect as it effectively resets Line to
0 when Line+1 reaches 80 . Effects such as
scrolling can be emulated by changing SL
dynamically.
MY I
Row Mirroring (MY) is implemented by reversing
the mapping order between COM electrodes and
RAM, i.e. the mathematical address generation
formula becomes:
Visually, the effect of MY is equivalent to flipping
the display upside down. The data stored in
display RAM are not affected by MY.
For the 1
Otherwise
For the 1
Otherwise
MPLEMENTATION
DDRESS
where MUX = CEN + 1
Line = SL
Line = Mod( Line +1, 80)
Line = Mod( SL + MUX-1 , 80 )
Line = Mod( Line-1 , 80 )
st
st
line period of each field
G
line period of each field
ENERATION
ES Specifications
© 1999 ~ 2003