uc1682 ETC-unknow, uc1682 Datasheet - Page 37

• Manufacturer Part Number: uc1682
• Description: 80 X 104rgb C-stn Lcd Controller-driver W/ 32-shade Per Dot, 12-bit Per Rgb
• Manufacturer: ETC-unknow

H
As summarized in the table below, UC1682
supports two parallel bus protocols, in either 8-bit
or 4-bit bus width, and three serial bus protocols.
* Connect unused control pins and data bus pins to V
P
The timing relationship between UC1682 internal
control signal RD, WR and their associated bus
actions are shown in the figure below.
The Display RAM read interface is implemented
as a two-stage pipe-line. This architecture
requires that, every time memory address is
modified, either in 8-bit mode or 4-bit mode, by
either Set CA, or Set RA command, a dummy
read cycle needs to be performed before the
actual data can propagate through the pipe-line
and be read from data port D[7:0].
Revision 0.6
ARALLEL
OST
S8 or S9
Bus Type
x
x
x
x
x
S8uc
8-bit
4-bit
Access
Width
I
NTERFACE
BM[1:0]
CS[1:0]
CS disable bus interface – CS can be used to disable Bus Interface Write / Read Access.
CD refers to CD transitions within valid CS window. CD = 0 means write command or read status.
CS / CD Sync / RESET can be used to initialize bus state machine (like 4 bits / S8 / S9).
RESET can be pin reset / soft reset / power on reset.
CD can be used to initialize the multi-byte input RGB format to/from on-chip SRAM mapping.
D[7:6]
D[5:4]
D[3:0]
WR0
WR1
I
NTERFACE
CD
Interface
Disable
CS
Data
Data
Data
8-bit
10
8080
___
WR
___
RD
__
__
Data
4-bit
0X
Init bus
00
–
state
Read/Write
Table 3: Host interfaces Summary
CS
–
–
–
Data
Data
Data
8-bit
11
CD 1<=>0
Init bus
Control/Data
6800
R/W
state
EN
DD
–
–
_
_
or V
Data
4-bit
Chip Select
0X
01
Designers can either use parallel bus to achieve
high data transfer rate, or use serial bus to create
compact LCD modules.
There is no pipeline in write interface of Display
RAM. Data is transferred directly from bus buffer
to internal RAM on the rising edges of write
pulses.
8-
UC1682 supports both 8-bit and 4-bit bus width.
The bus width is determined by pin BM[1].
4-bit bus operation exactly doubles the clock
cycles of 8-bit bus operation, MSB followed by
LSB, including the dummy read, which also
requires two clock cycles. The bus cycle of 4-bit
mode is reset each time CD pin changes state
(when CS is active).
–
SS
BIT
& 4-
CD 1=>0
mapping
init color
S8 (4wr)
BIT
00
10
B
US
O
80x104RGB CSTN Controller-Driver
D0=SCK, D3=SDA
PERATION
RESET
Init bus
Write Only
S8uc (3wr)
state
Serial
–
–
–
00
11
mapping
UC1682
init color
RESET
S9 (3wr)
01
1X
–
35