uc1682 ETC-unknow, uc1682 Datasheet - Page 17

• Manufacturer Part Number: uc1682
• Description: 80 X 104rgb C-stn Lcd Controller-driver W/ 32-shade Per Dot, 12-bit Per Rgb
• Manufacturer: ETC-unknow

C
(1) W
UC1682 will convert input RAM data to 12-bits of RGB data. Please refer to command (22) Set Color Mode
for detail data write sequence. The format of 12 bits RGB data is as following:
(2) R
Each RGB triplet is stored as 12-bit in the display RAM. Each 12 bits RGB data takes 2 RAM read cycles.
The data read will start with the high byte D[11:4] and then low byte {D[3:0],4’b0000}. The read out RGB
data is after-dither for 56K color and 221K color mode and after-extension for 256 color mode.
Write/Read Data Byte (command 1/2) operation uses internal Row Address register (RA) and Column
Address register (CA). RA and CA can be programmed by issuing Set Row Address and Set Column
Address commands. If wrap-around (WA, AC[0]) is OFF (0), CA will stop incrementing after reaching the CA
boundary, and system programmers need to set the values of RA and CA explicitly. If WA is ON (1), when
CA reaches end of column address, CA will be reset to 0 and RA will be increased or decreased, depending
on the setting of Row Increment Direction (RID, AC[2]). When RA reaches the boundary of RAM (i.e. RA = 0
or 79), RA will be wrapped around to the other end of RAM and continue.
(3) G
Status flag definitions:
ID:
MX: Status of register LC[1], mirror X.
MY: Status of register LC[2], mirror Y.
WA: Status of register AC[0]. Automatic column/row wrap around.
DE:
WS : OTP Command Succeeded
OD: OTP Option (Yes/No)
OS : OTP action status
(4) S
Set SRAM column address for read/write access. CA is counted in RGB triplets, not individual SEG
electrode.
CA value range: 0~103
Revision 0.6
R3
D11
OMMAND
Set Column Address MSB CA[6:4]
Set Column Address LSB CA[3:0]
EAD
Provide access to ID pin connection status.
ET
ET
Display enable flag. DE=1 when display is enabled
RITE
R2
C
S
D10
D
OLUMN
TATUS
D
ATA
ATA
R1
D
R
Get Status
Write data
Read data
F
ESCRIPTION
T
Action
Action
Action
Action
ROM
A
O
D9
1st Read
DDRESS
R0
D
ISPLAY
D
ISPLAY
G4
D8
M
EMORY
M
G3
EMORY
D7
G2
C/D W/R D7
C/D W/R D7
C/D W/R D7
C/D W/R D7
D6
1
1
G1
0
0
0
G
0
1
0
0
1
G0
D5
ID
0
0
B2
D4
MX MY WA DE WS OD OS
D6
D6
D6
D6
0
0
8bits data write to SRAM
B1
8bits data from SRAM
D5
D5
D5
D5
0
0
2nd Read
D3
B0
D4
D4
D4
D4
0
1
0
D2
CA3 CA2 CA1 CA0
D3
D3
D3
D3
-
80x104RGB CSTN Controller-Driver
B
CA6 CA5 CA4
0
D2
D2
D2
D2
D1
D1
D1
0
D1
D1
D0
D0
D0
D0
D0
0
UC1682
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