uc1682 ETC-unknow, uc1682 Datasheet
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H -V IGH 80 x 104RGB C-STN LCD Controller-Driver w/ 32-shade per dot, 12-bit per RGB (Dither 221K) ES Specifications Revision 0 OLTAGE IXED IGNAL U LTRA The Coolest LCD Driver. Ever!! IC August 11, 2003 C HIP ...
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... LCD DISPLAY CONTROLS............................................................................................. 32 HOST INTERFACE .......................................................................................................... 35 DISPLAY DATA RAM ...................................................................................................... 42 RESET & POWER MANAGEMENT ................................................................................ 45 ABSOLUTE MAXIMUM RATINGS .................................................................................. 49 SPECIFICATIONS............................................................................................................ 50 AC CHARACTERISTICS ................................................................................................. 51 PHYSICAL DIMENSIONS................................................................................................ 58 ALIGNMENT MARK INFORMATION.............................................................................. 59 PI INFORMATION ............................................................................................................ 60 PAD COORDINATES....................................................................................................... 61 TRAY INFORMATION...................................................................................................... 65 COF INFORMATION ........................................................................................................ 66 REVISION HISTORY........................................................................................................ 68 Revision 0 ABLE OF ONTENT UC1682 80x104RGB CSTN Controller-Driver 1 ...
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... In addition to low power COM and SEG drivers, UC1682 contains all necessary circuits for high-V LCD power supply, bias voltage generation, timing generation and graphics data memory. Advanced circuit design techniques are ...
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... RDERING NFORMATION Part Number Versions UC1682xHCZ Gold Bumped Die with PI UC1682tHCZ Gold Bumped Die with PI UC1682xFBZ COF UC1682tFBZ COF Convention note: Grayed-out contents are functions not available yet. 2 Description Without OTP option With OTP option Without OTP option with OTP option ES Specifications © ...
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... UPPORT PPLICATIONS These devices are not designed for use in life support appliances, or systems where malfunction of these products can reasonably be expected to result in personal injuries. Customer using or selling these products for use in such applications their own risk. Revision 0.6 UC1682 80x104RGB CSTN Controller-Driver 3 ...
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U C LTRA HIP High-Voltage Mixed-Signal LOCK IAGRAM COLUMN ADDRESS GENERATOR POWER-ON & RESET CONTROL CLOCK & TIMING GEN. CONTROL & STATUS REGISTER COMMAND HOST INTERFACE 4 DISPLAY DATA RAM DISPLAY DATA LATCHES LEVEL SHIFTERS SEG DRIVERS ...
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... V BX BX+ pin. Merge ITO traces between B1/2x and V in COG optional. It can be connected between When C is used, keep the trace resistance under 300 . SS L UC1682 80x104RGB CSTN Controller-Driver /V . DD2 DD3 and DD2 DD3 DD2 DD3 pin. When not ...
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... CS0 chip is not selected, D[7:0] will be high impedance. When RST=”L”, all control registers are re-initialized by their default states. Since UC1682 has built-in Power-ON Reset and Software Reset command, RST pin is not required for proper chip operation. RST Filter has been included on-chip. There is no need for external RC noise filter ...
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... COM and 0~311 for SEG. Revision 0.6 Description V LCD D O IGH OLTAGE RIVER UTPUT ISC INS . These pins are connected to the main main V externally. DDX DD UC1682 80x104RGB CSTN Controller-Driver bus on chip. They DD power to the chip not DD 7 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC R COG L ECOMMENDED AYOUT Users can use either OTP control (through TST4 pin) or Please refer to the following figures Example for TST4 COG layout when using OTP control to ...
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... VLCD NC Notes for V with COG: DD The V =1.8V-typ operation condition of UC1682 should be met under all LCM formats. Unless V DD ITO trances can each be controlled lower, otherwise V on-chip V to drop below V =1.7V during high speed data write condition. Therefore, for COG separation is not suitable for pure ITO based COG designs ...
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... UC1682 contains registers which control the chip operation. These registers can be modified by commands. The following table is a summary of the control registers, their meanings and their default values. Commands supported by UC1682 will be described in the next two sections. First, a summary table, followed by a detailed instruction-by-instruction description. ...
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... CEN = the actual number of pixel rows on the LCD - 1 CEN DEN DST+ 9 Revision 0.6 Description 0: 8-shade mode 1: 32-shade Mode 0: Disable Dither Function 1: Enable Dither Function 0: Column (CA) first 1: Row (RA) first when CUM=1, CA increment on write only, wrap around suspended 0 : Disable 1 : Enable UC1682 80x104RGB CSTN Controller-Driver 11 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC Name Bits Default LC 10 090H LCD Control: LC[0]: Enable the first FLx2 lines in partial display mode (Default OFF). LC[1]: MX, Mirror X. SEG/Column sequence inversion (Default: OFF) LC[2]: MY, Mirror Y. ...
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... C T OMMAND ABLE The following is a list of host commands supported by UC1682 C/D: 0: Control, 1: Data W/R: 0: Write Cycle, 1: Read Cycle # Useful Data bits – Don’t Care Command C/D W Write Data Byte Read Data Byte Get Status 0 1 Set Column Address LSB ...
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... Other than commands listed above, all other bit patterns may result in undefined behavior. x The OTP commands listed above should only be used with OTP version of UC1682. x Command 39~42 are shared with command 32~35, and they have exactly the same code. The interpretation of these four commands depends on register OTPC[3]. When OTPC[3]=0, they are ...
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... D M RITE ATA O ISPLAY EMORY Action Write data UC1682 will convert input RAM data to 12-bits of RGB data. Please refer to command (22) Set Color Mode for detail data write sequence. The format of 12 bits RGB data is as following: D11 D10 ( ...
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U C LTRA HIP High-Voltage Mixed-Signal IC ( EMPERATURE OMPENSATION Action Set Temperature Comp. TC[1:0] Set V temperature compensation coefficient (%-per-degree-C) BIAS Temperature compensation curve definition: o 00b= -0.05%/ C 01b= -0.10%/ ( ...
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... PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 S for more detail. OLTAGE ETTING C/D W C/D W UC1682 RA6 RA5 RA4 LC9 LC8 AC2 AC1 AC0 17 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC (14 IXED INES Action Set Fixed Lines FL [3:0] The fixed line function is used to implement the partial scroll function by dividing the screen into scroll and fixed ...
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... When DC[2] is set to 0, the IC will put itself into Sleep mode. All drivers, voltage generation circuit and timing circuit will be halted to conserve power. When DC[2] is set to 1, UC1682 will first exit from Sleep mode, restore the power and then turn on COM drivers and SEG drivers. There is no other explicit user action or timing sequence required to enter or exit the Sleep mode ...
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... RAM column address so this function will only take effect after rewriting the RAM data. LC[0] controls whether the soft icon section (0~ 2xFL) is display or not during partial display mode. (21 OLOR ATTERN Action Set Color Pattern LC [5] UC1682 supports on-chip swapping of R LC[5] SEG1 SEG2 SEG3 ...
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... D[7: D[7: UC1682 LC7 LC6 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC No-Dither Options: DC[4]=0b disables dither function. Refer to (18) Set Display Enable for more information. LC[7:6] = 00b ( RRR-GGG-BB, 256 color ) One byte of input data is extended and stored to ...
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... Action Set AC[3]=1 CR=CA This command is used for set cursor update mode function. When cursor update mode is set, UC1682 will update register CR with the value of register CA. The column address CA will increment with write RAM data operation but the address wraps around will be suspended no matter what WA setting is. However, the column address will not increment in read RAM data operation. The set cursor update mode can be used to implement “ ...
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... RAM to each COM electrodes. The image displayed by each pixel row is therefore not affected by the setting of these three registers. When LC[9]=1, two partial display modes are possible with UC1682: LC[8]=1: ON-OFF only, ultra-low-power mode (if Mux-Rate U 32, set BR=5). LC[8]=0: Full gray shade low power mode (BR and PM stays the same) When LC[9:8]=11b, the Mux-Rate is narrowed down to just the range between DST and DEN ...
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... DDRESS C/D W WPC1[7:0] register parameter A DDRESS C/D W WPP1 register parameter C/D W UC1682 80x104RGB CSTN Controller-Driver AC4 25 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC Auto-increment order = 0 MX=0 RID = 0 (WPP0,WPC0) Auto-increment order = 1 MX=0 RID = 0 (WPP0,WPC0) Auto-increment order = 0 MX=0 RID = 1 (WPP0,WPC0) Auto-increment order = 0 MX=1 RID ...
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... Auto-increment order = 1 MX=0 RID = 1 (WPP0,WPC0) Auto-increment order = 1 MX=1 RID = 0 (WPP1,103-WPC1) Auto-increment order = 0 MX=1 RID = 1 (WPP1,103-WPC1) Auto-increment order = 1 MX=1 RID = 1 (WPP1,103-WPC1) Revision 0.6 UC1682 80x104RGB CSTN Controller-Driver (WPP1,WPC1) (WPP0,103-WPC0) (WPP0,103-WPC0) (WPP0,103-WPC0) 27 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC (37) S OTP C ET ONTROL Action Set OTPC (Double byte command) This command is for OTP operation control: OTPC[2:0] : OTP command 000 : Sleep 010 : OTP Erase 1XX : For ...
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... UC1682 via registers CEN, DST, DEN, and partial display control LC[9:8]. Combined with low power partial display mode and a low bias ratio of 5, UC1682 can support wide variety of display control options. For example, when a system goes into stand-by mode, a large portion of LCD screen can be turned off to conserve power ...
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U C LTRA HIP High-Voltage Mixed-Signal UICK EFERENCE LCD VLCD-PM relationship for different BR setting ( 4.474 ...
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... RC time constant should be roughly 0.2~1sec 1M³Ÿ 330K Ÿ 10nF ~ 0.1uF is the recommended default value (not required for OTP version). BIAS Revision 0.6 UC1682 80x104RGB CSTN Controller-Driver VB0+ SB0+ CB0 VB0- SB0- VB1+ SB1+ CB1+ CB1 (OPTIONAL) VB1- 30pf for ...
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... Driver Enable is controlled by the value of DC[2] via Set Display Enable command. When DC[2] is set to OFF (logic “0”), both COM and SEG drivers will become idle and UC1682 will put itself into Sleep mode to conserve power. When DC[2] is set to ON, the DE flag will become “ ...
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... C COM AYOUT ONSIDERATIONS FOR SIGNALS Since the COM scanning pulse of UC1682 can be as short as 30µ critical to control the RC delay of COM signal to minimize distortion of COM scanning pulse. For the best image quality, limit the worst case of RC delay of COM signal as calculated below. ...
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U C LTRA HIP High-Voltage Mixed-Signal IC RAM W/R POL COM1 COM2 COM3 SEG1 SEG2 F IGURE 34 5: COM and SEG Driving Waveform © 1999 ~ 2003 ES Specifications ...
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... B BIT BIT US UC1682 supports both 8-bit and 4-bit bus width. The bus width is determined by pin BM[1]. 4-bit bus operation exactly doubles the clock cycles of 8-bit bus operation, MSB followed by LSB, including the dummy read, which also requires two clock cycles. The bus cycle of 4-bit mode is reset each time CD pin changes state (when CS is active) ...
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... Parallel Interface & Related Internal Signals IGURE S I ERIAL NTERFACE UC1682 supports three serial modes, one 4-wire SPI mode (S8), one compact 3/4-wire mode (S8uc) and one 3-wire SPI mode (S9). Bus interface mode is determined by the wiring of the BM[1:0] and D[7:6]. See table in last page for more detail. S8 (4- ...
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... SCK pulse. By sending CD information explicitly in the bit stream, control pin CD is not used, and should be connected to either V or CS1 for each byte of data/command is recommended but optional 7.c: 3-wire Serial Interface (S9) UC1682 The toggle of CS0 ...
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... IORQ GND F 9: 8080/4bit parallel mode reference circuit IGURE 38 VDD VDD D7-D0 CD WR0(WR) WR1(RD) CS0 UC1682 DECODER CS1 VDD RST ID VDD BM1 BM0 VSS VDD VDD D7 D3-D0 CD WR0(WR) WR1(RD) CS0 UC1682 DECODER CS1 VDD RST ID BM1 BM0 VSS © 1999 ~ 2003 ES Specifications ...
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... F 11: 6800/4bit parallel mode reference circuit IGURE Revision 0.6 80x104RGB CSTN Controller-Driver VDD VDD D7-D0 CD WR0(R/W) WR1(E) CS0 UC1682 DECODER CS1 VDD RST ID VDD BM1 BM0 VSS VDD VDD D7 D3-D0 CD WR0(R/W) WR1(E) CS0 UC1682 DECODER CS1 VDD RST VDD ID BM1 BM0 VSS UC1682 39 ...
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... SPI (S8uc) serial mode reference circuit IGURE 40 VDD D7 VDD D6 SCK(D0) SDA(D3) CD WR0 WR1 CS0 UC1682 DECODER CS1 VDD RST ID BM1 BM0 VSS VDD VDD D7 VDD D6 SCK(D0) SDA(D3) CD WR0 WR1 CS0 UC1682 VDD RST ID CS1 BM1 BM0 VSS © 1999 ~ 2003 ES Specifications ...
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... V DD RST pin is optional. When RST pin is not used, connect the pin Revision 0.6 80x104RGB CSTN Controller-Driver VDD D7 SCK(D0) SDA(D3) WR0 WR1 CS0 DECODER CS1 VDD RST ID VDD BM1 BM0 for “L” UC1682 VDD VDD UC1682 VSS 41 ...
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U C LTRA HIP High-Voltage Mixed-Signal RAM ISPLAY ATA D O ATA RGANIZATION The input display data (depend on color mode) are stored to a dual port static RAM (RAM, for Display Data RAM) organized as 80x104X12. ...
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... AC[2] will result the data write starting either from row ) WPP0, WPC0 for the initial column WPP0 WPP1 address either from to WPC0 MC-WPC1 Example 2: AC[2:0] = 111 103 (WPP0, WPC0) (WPP1,WPC1) UC1682 80x104RGB CSTN Controller-Driver to or from ( WPC0 WPC1 MC ...
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U C LTRA HIP High-Voltage Mixed-Signal IC Row Adderss 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 38H 39H ...
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... COM LCD BIAS and SEG drivers from their idle states. When ON exiting Sleep or Reset mode, COM and SEG ON drivers will not be activated until UC1682 internal ON voltage sources are restored to their proper values. OFF UC1682 M ODE . To drain these ...
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... OWER P EQUENCE UC1682 power-up sequence is simplified by built-in “Power Ready” flags and the automatic invocation of System-Reset command after Power-ON-Reset . System programmers are only required to wait before the CPU starting to issue commands to UC1682. No additional time sequences are required between enabling the charge pump, turning on the display drivers, writing to RAM or any other commands ...
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... Set Display Enable UC1682 80x104RGB CSTN Controller-Driver Comments Wait 5~10ms after Ignore OTP value Set up LCD format specific parameters, MX, MY, etc. Fine tune for power, flicker, contrast, and shading. LCD specific operating voltage setting ...
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U C LTRA HIP High-Voltage Mixed-Signal -OFF XTENDED ISPLAY Type C/D W – – – – – – – – – ...
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... Digital input signal IN T Operating temperature range OPR T Storage temperature STR Notes 1. V based Stress beyond ranges listed above may cause permanent damages to the device. Revision 0 +75 C) UC1682 80x104RGB CSTN Controller-Driver Min. Max. Unit -0.3 +4.0 V -0.3 +4.0 V -0.3 +4.0 V -0.3 +12 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC S PECIFICATIONS DC C HARACTERISTICS Symbol Parameter V Supply for digital circuit DD V Supply for bias & pump DD2/3 V Charge pump output LCD V LCD data voltage D V Input logic ...
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... DH80 t OD80 C) Description Condition 8 bits bus (read) (write) 4 bits bus (read) (write) 4 bits 4 bits 8 bits bus (read) (write) 4 bits bus (read) (write 100pF L UC1682 80x104RGB CSTN Controller-Driver t t CSH80 CSSD80 Min. Max. Units 0 – – ns 140 80 140 80 70 – – ...
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U C LTRA HIP High-Voltage Mixed-Signal IC o (1. 2.5V, Ta= –30 to +85 DD Symbol Signal t Address setup time AS80 CD t Address hold time AH80 t System cycle time CY80 t Pulse width 8 ...
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... DS68 DH68 t OD68 C) Description Condition 8 bits bus (read) (write) 4 bits bus (read) (write) 4 bits 4 bits 8 bits bus (read) (write) 4 bits bus (read) (write 100pF L UC1682 80x104RGB CSTN Controller-Driver t t CSH68 CSSD68 Min. Max. Units 0 – – ns 140 80 140 80 70 – ns ...
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U C LTRA HIP High-Voltage Mixed-Signal IC o (1. 2.5V, Ta= –30 to +85 DD Symbol Signal t CD Address setup time AS68 t Address hold time AH68 T System cycle time CY68 t WR1 Pulse width ...
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... Data hold time DHS8 t CSSAS8 t CS1/CS0 Chip select setup time CSSDS8 t CSHS8 Revision 0.6 t AHS8 t CYS8 t HPWS8 t DHS8 C) Description Condition C) Description Condition UC1682 80x104RGB CSTN Controller-Driver t t CSHS8 CSSDS8 Min. Max. Units 0 – – – – – – ...
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U C LTRA HIP High-Voltage Mixed-Signal IC CS0 CS1 t CSS9 t WLS9 SCK t DSS9 SDA F 20: Serial Bus Timing Characteristics (for S9) IGURE o (2. 3.3V, Ta= –30 to +85 DD Symbol Signal t ...
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... RST o (1. 3.3V, Ta= –30 to +85 DD Symbol Signal t RST Reset low pulse width RW Revision 0 21: Reset Characteristics IGURE C) Description Condition UC1682 80x104RGB CSTN Controller-Driver Min. Max. Units 500 – ...
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U C LTRA HIP High-Voltage Mixed-Signal HYSICAL IMENSIONS OORDINATES IZE 13.944mm x 1.494mm HICKNESS 0.5mm B : UMP HEIGHT 17µm ±1µm (within die ...
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... D-Right Mark Y X -612.1 5535.4 -612.1 -667.2 5547.4 -667.2 -633.7 5523.9 -633.7 -645.7 5558.9 -645.7 -639.7 5541.4 -639 OTP P ECTION OR UC1682 U-Right Mark D-Right Mark Y Y SiON / (TBD)K > Metal3 / 9K > ROCESS ROSS ECTION 59 ...
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U C LTRA HIP High-Voltage Mixed-Signal NFORMATION HICKNESS 3.6 ± 0.4 µ INIMUM EPARATION UMP O DGE OF OLYIMIDE L : AYER 20 µm 60 ©1999~2003 ...
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... VB1+ 2548 116 VB1+ 2618 117 VB1+ 2688 118 SB1+ 2758 119 VB1- 2976 120 VB1- 3046.9 UC1682 -645 -645 -645 -645 -645 -645 -645 -645 -645 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC # Pad Name X Y 121 VB1- 3116.9 -645.4 122 VB1- 3186.9 -645.4 123 VB1- 3256.9 -645.4 124 VB1- 3479.7 -645.4 125 VB1- 3550.0 -645.4 126 VB1- 3620.0 -645.4 127 VB1- 3690.0 -645.4 ...
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... SEG184 -1142.2 24.5 123 369 SEG185 -1183.7 24.5 123 370 SEG186 -1225.2 24.5 123 371 SEG187 -1266.7 24.5 123 372 SEG188 -1308.2 UC1682 1264.8 628.6 24.5 123 1223.3 628.6 24.5 123 1181.8 628.6 24.5 123 1140.3 628.6 24.5 123 1098.8 628.6 24.5 123 1057.3 628.6 24 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC # Pad Name X Y 373 SEG189 -1349.7 628.6 374 SEG190 -1391.2 628.6 375 SEG191 -1432.7 628.6 376 SEG192 -1474.2 628.6 377 SEG193 -1515.7 628.6 378 SEG194 -1557.2 628.6 379 SEG195 -1598.7 628.6 ...
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... T I RAY NFORMATION Revision 0.6 UC1682 80x104RGB CSTN Controller-Driver 65 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC COF I NFORMATION 7.733 (IC Center) 1.NC 2.VLCD 3.VBO- 4.VB1- 5.VB1+ 6.VB0+ 7.VDD 8.VDD2,3 9.VSS 10.ID 11.VBIAS 12.TST4 13.BM1 14.BM0 15.WR1 16.WR0 17.CD 18.CS0 19.CS1 20.RST 21.DO 22.D1 23.D2 24.D3 25.D4 26.D5 27.D6 ...
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... 396 28 D7 397 29 NC 398 Revision 0.6 80x104RGB CSTN Controller-Driver 0.8 NC COM 79 COM 77 0.1 COM 3 COM SEG 1 SEG 306 SEG 307 SEG 308 SEG 309 SEG 310 SEG 311 SEG 312 NC NC COM 2 COM 4 COM 78 COM 80 NC Input Output UC1682 0.8 67 ...
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U C LTRA HIP High-Voltage Mixed-Signal EVISION ISTORY Version 0.0 0.1 Figure 15 “Reference Power-Up Sequence” is updated for OTP. 0.6 (Section “Reset & Power Management”, page 46; “Power Up” table, page 47.) 68 Contents Preliminary specification ...