uc1682 ETC-unknow, uc1682 Datasheet - Page 19

• Manufacturer Part Number: uc1682
• Description: 80 X 104rgb C-stn Lcd Controller-driver W/ 32-shade Per Dot, 12-bit Per Rgb
• Manufacturer: ETC-unknow

(10) S
Set SRAM row address for read/write access.
Possible value = 0~79
(11) S
Program V
Effective range: 0 ~ 255
(12) S
This command is used to enable partial display function.
LC[9:8] : 0Xb: Disable Partial Display, Mux-Rate = CEN+1 (DST, DEN not used.)
(13) S
Program registers AC[2:0] for RAM address control.
AC[0]: WA, Automatic column/row wrap around.
AC[1]: Auto-Increment order
AC[2]: RID, row address (RA) auto increment direction ( 0/1 = +/- 1 )
AC[2:0] controls the auto-increment behavior of CA and RA. When Window Program is enabled (AC[4]=ON),
see command description (32) ~ (36) for more details. If WPC[1:0] and WPP[1:0] values are the default
values, the behavior of CA, RA auto-increment will be the same, no matter what the setting of AC[4] is.
Revision 0.6
Set Partial Display Enable LC [9:8]
0: CA or RA (depends on AC[1]= 0 or 1) will stop incrementing after reaching boundary
1: CA or RA (depends on AC[1]= 0 or 1) will restart, and RA or CA will increment by one step.
0 : column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+/-1).
1 : row (RA) increment (+/-1) first until RA reach RA boundary, then CA will increment by (+1).
When WA=1 and CA reaches CA boundary, RID controls whether row address will be adjusted by
+1 or -1.
Set V
Set Row Address MSB RA [6:4]
Set Row Address LSB RA [3:0]
ET
ET
ET
ET
(Double byte command)
R
V
P
RAM A
10b: Enable Partial Display, Mux-Rate = CEN+1
11b: Enable Partial Display, Mux-Rate = DEN-DST+1+LC[0]x2xFL
BIAS
BIAS
ARTIAL
OW
BIAS
Potentiometer. PM [7:0]
P
A
Set AC [2:0]
Potentiometer (PM[7:0]). See section LCD V
OTENTIOMETER
DDRESS
DDRESS
Action
Action
Action
Action
D
ISPLAY
C
ONTROL
C
ONTROL
C/D W/R D7
C/D W/R D7
C/D W/R D7
C/D W/R D7
0
0
0
0
0
0
0
0
0
0
0
0
PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0
0
0
1
1
1
D6
D6
D6
D6
1
1
0
0
0
OLTAGE
D5
D5
D5
D5
1
1
0
0
0
S
ETTING
D4
D4
D4
D4
0
1
0
0
0
RA3 RA2 RA1 RA0
D3
D3
D3
D3
0
1
0
-
for more detail.
80x104RGB CSTN Controller-Driver
RA6 RA5 RA4
AC2 AC1 AC0
D2
D2
D2
D2
1
0
LC9 LC8
D1
D1
D1
D1
0
D0
D0
D0
D0
1
UC1682
17