hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 40

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

POSITION
31-16
12-9
BIT
8-5
15
14
13
4
3
2
1
0
Not Used
Reserved
False Lock Detect
Enable
Frequency Sweep
Mode
Verify State Length
False Lock Sweep
Lock Detector Control
Microprocessor
Acquisition/Track
Select
Microprocessor Lock
Reserved
Microprocessor
Frequency Sweep
Enable
FUNCTION
3-40
TABLE 37. ACQUISITION/TRACKING CONTROL REGISTER
No programming required.
Set to 0 for proper operation.
This bit enables the false lock detection during the verify state of state machine controlled acquisition.
The overflow of the False Lock Accumulator before the Integration Counter forces the false lock state. If
disabled, the overflow of the False Lock Accumulator has no effect on state machine operation.
0 = Disable False Lock.
1 = Enable False Lock.
Note: The false Lock Detector is designed for false lock detection on square wave data. For shaped
waveforms false lock detection should be disabled or frequency error should be used.
This bit selects whether stepped or continuous frequency sweep mode is used (see Lock Detector Sec-
tion).
0 = Stepped Frequency Sweep (provided for microprocessor controlled acquisition mode).
1 = Continuous Frequency Sweep.
These bits set the number of integration cycles over which carrier lock must be maintained before the
Lock State is declared. The verify state is used to make sure that lock detection was not the result of noise
or false lock. The 4-bit value programmed here sets the verify state from 0 to 15 Integration Periods.
These bits set the duration of forced frequency sweep before returning to the acquisition state. When
continuous frequency sweep mode is selected, the programmed number represents the number of Lock
Accumulator integration cycles to sweep before returning to the acquisition state. In stepped frequency
sweep mode, the number represents the number of loop filter compute cycles over which to enable the
sweep input to the lag accumulator.
This bit selects whether the acquisition/tracking process is controlled externally by a microprocessor or
internally by the state machine. If microprocessor control is chosen, the lock detect accumulator
integrates for the programmed period of time and ignores accumulator roll over, if any. The Lock Detector
Accumulator halts after each Integration Period and waits to be restarted by the microprocessor. In
addition, the microprocessor must select the acquisition/tracking parameters, as well as enable the
Frequency Sweep Block.
0 = Microprocessor Control.
1 = Internal State Machine Control.
0 = Track Parameters Chosen.
1 = Acquisition Parameters Chosen.
This bit controls the state of the lock bit (STATUS6) in the status output STATUS6-0 (see Output Select
Section). In addition, this bit sets the internal state machine to the locked state when Lock Detector
Control is switched from microprocessor control to state machine control. See Table 46 for the STATUS
bit information.
Set to zero for proper operation.
This bit is used to enable the output of the Frequency Sweep Block to the lag path of the Symbol Tracking
Loop Filter. This bit is only used under microprocessor control of the Lock Detector.
DESTINATION ADDRESS = 23
HSP50210
DESCRIPTION