hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 25

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

Serial Output Controller
The frequency correction terms generated by the Symbol
and Carrier Loop Filters are output through two separate
serial interfaces. The symbol frequency offset used to close
the symbol Tracking Loop is output via the SOF and
SOFSYNC outputs. The carrier offset frequency used to
close the Carrier Tracking Loop is output via the COF and
COFSYNC outputs.
The serial output timing, identical for both of the loop filter
outputs, is shown in Figure 18. The data word is output MSB
first starting with the first rising edge of either CLK or
SLOCLK that follows the assertion of sync (COFSYNC or
SOFSYNC). The HSP50210 is configured to output the
serial data with either CLK or SLOCLK (see Serial Output
Configuration Control Registers bit 7, Table 41). The
SLOCLK output is a programmable sub-multiple of CLK
which is provided for applications requiring a slower serial
clock. In applications where the HSP50210 is used with the
HSP50110, both parts must be supplied with the same CLK
and the HSP50210 is configured to use CLK as the serial
clock. The serial output can be configured for word
containing from 8 to 40 bits.
COUNTER FINISHES
ACCUMULATOR
PHASE ERROR
INTEGRATION COUNTER
INTEGRATION
3-25
BEFORE
FINISHES BEFORE
ACCUMULATOR
PHASE ERROR
FIGURE 18. ACQUISITION/TRACKING STATE DIAGRAM
LOCK
LOCK COUNTER
FALSE
DONE
HSP50210
FINISHES BEFORE
COUNTER DONE
ACCUMULATOR
PHASE ERROR
INTEGRATION
AND VERIFY
COUNTER
SEARCH
FALSE
LOCK
LOCK COUNTER
ACCUMULATOR
FINISHES BEFORE
FALSE LOCK
ACCUMULATOR
PHASE ERROR
BEFORE
INTEGRATION
NOTE: COFSYNC and SOFSYNC shown Configured as active
“High”.
Output Selector
The output selector determines which internal signals are
multiplexed to the AOUT9-0 and BOUT9-0 outputs. Fifteen
different output options are provided: ISOFT(2:0), QSOFT(2:0),
IEND(7:1), QEND(7:1), AGC(7:1), MAG(7:0), Phase(7:0),
FREQERR(7:1), GAINERR(7:1), BITPHERR(7:1),
CARPHERR(7:1), LKACC(6:0), LKCNT(6:0), NCOCOS(9:0),
and STATUS (6:0). These are detailed in the Output Selector
Configuration Control Register, bits 0-3 (see Table 42).
COUNTER
COFSYNC/
PHASE ERROR ACCUMULATOR
FINISHES BEFORE
INTEGRATION COUNTER
SOFSYNC
FIGURE 19. SERIAL OUTPUT TIMING FOR COF AND SOF
FALSE
LOCK COUNTER
NOT DONE
SLOCLK
CLK/
COF/
SOF
VERIFY
INTEGRATION COUNTER
FINISHES BEFORE
PHASE ERROR ACCUMULATOR
OUTPUTS
INTEGRATION COUNTER
FINISHES BEFORE
PHASE ERROR
ACCUMULATOR AND
VERIFY COUNTER
NOT DONE
MSB
MSB