hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 18

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

In applications where Phase Error terms are generated
faster than the processing rate of the Carrier Loop Filter, an
error accumulator is provided to accumulate errors until the
loop filter is ready for a new input. Phase Error terms are
generated at the rate I/Q samples are input to the Cartesian
to Polar Converter. However, the Carrier Loop Filter can not
accept new input faster than CLK/6 since six CLK(f
clock edges are required to complete its processing cycle. If
the error accumulator is not used and the I/Q sample rate
exceeds CLK/6, error terms will be missed.
NOTE: The carrier Phase Error terms input to the loop filter are
only generated from the end-symbol samples when the output
of the I&D filter is selected for input to the Cartesian-to-Polar
converter.
NOTE: The loop filter lead gain term must be scaled accordingly
if the accumulator is used.
Carrier Loop Filter
The Carrier Loop Filter is second order lead/lag filter as
shown in Figure 14. The loop filter is similar to the Symbol
Tracking Loop Filter except for the additional terms from the
AFC Loop Filter and the Frequency Sweep Block. The
output of the Lag Accumulator is summed with the weighted
Phase Error term on the lead path to produce a frequency
control term. The Carrier Loop Filter is configured for
operation by the Control Registers described in Tables 20
to 27.
BOUNDARY
CONSTELLATION
MODULATION
DECISION
FIGURE 14. PHASE ERROR DETECTOR OPERATION (QPSK)
REGION
TABLE 8. BASIC PHASE ERROR DETECTOR SETTINGS
180
QPSK
8-PSK
TYPE
BPSK
PHASE ROTATION BY 45
CW
E
o
ACTUAL
PROJECTION OF PHASE ERROR ( E
POINT
X
INPUT TO CARTESIAN/POLAR CONVERTER
-90
90
X
X
22.5
45
o
o
0
0
Q
o
o
180
OFFSET
o
PHASE
(00 HEX)
(00 HEX)
o
(20 HEX)
X
(10 HEX)
E
o
45
I
o
0
o
o
3-18
X
X
Q
-90
90
BOUNDARY
DECISION
REGION
1 (left shift 1)
2 (left shift 2)
3 (left shift 3)
o
o
0 (no shift)
FACTOR
45
SHIFT
X
X
o
MULTIPLICATION BY 4
I
BOUNDARY
DECISION
0
REGION
)
(MODULO 2
o
ABOUT 0
EXPECTED
CONSTELLATION
POINT
-22.5
Q
22.5
PHASE ER-
o
o
RANGE
o
ROR
CLK
X
180
90
45
22
)
E
I
)
0
o
HSP50210
The Carrier Tracking Loop is closed by using the loop filter
output to control the NCO or VCO used to down convert the
channel of interest. In basic configurations, the frequency
correction term controls the Synthesizer NCO in the
HSP50110 Digital Quadrature Tuner via the COF and
COFSYNC pins of the HSP50210’s serial interface (see
Serial Output Section). In applications where the carrier
tracking is performed using the NCO on board the
HSP50210, the loop filter output is fed to the on-board NCO
as a frequency control.
The gain for the lead and lag paths of the Carrier Loop Filter
are set through a programmable mantissa and exponent.
The mantissa is a 4-bit value which weights the loop filter
input from 1.0 to 1.9375. The exponent defines a shift factor
that provides additional weighting from 2
the loop gain mantissa and exponent provide a gain range
between 2
Lead/Lag Gain = (1.0+M*2
where M = a 4-bit binary number from 0 to 15, and E is
a 5-bit binary value ranging from 0 to 31. For example, if
M = 0101 and E = 00110, the Gain = 1.3125*2
gain mantissa and exponent are set in the Carrier Loop Gain
Control Registers (see Tables 24 - 25).
The Phase Error input to the Carrier Loop Filter is an 8-bit
fractional two’s complement number between ~1.0 to -1.0
(Format -2
for BPSK, QPSK and 8-PSK. If minimum loop gain is used,
the Phase Error is shifted in significance by 2
maximum loop gain, the Phase Error is passed almost
unattenuated. The output of the Carrier Loop filter is a 40-bit
fractional two’s complement number between ~1.0 and -1.0
(Format -2
the 32 MSBs of the loop filter output represent the
frequency control word needed to adjust the down
converting NCO for phase lock. Tables 9 and 10 illustrate
the bit weighting of the Carrier Loop Filter into the NCO for
both tracking and acquisition sweep modes.
A limiter is provided on the Carrier lag accumulator output to
keep frequency tracking within a user defined range (see
Tables 22 - 23). If the lag accumulator exceeds either the
upper or lower limit the accumulator is loaded with the limit.
For additional loop filter control, the Carrier Loop Filter
output can be frozen by asserting the FZ_CT pin which nulls
the Phase Error term into the loop filter. Also, the lag
accumulator can be initialized to a particular value via the
Microprocessor Interface as described in Table 27 and can
be read via the microprocessor interface as described in
“Reading from the Microprocessor Interface Section”.
-32
0
0
. 2
. 2
and
-1
-1
2
2
-2
-2
~
2
2
1.0 as given by,
-3
-3
2
..... 2
-4
2
-5
-4
-39
2
)*2
-6
2
-(32 -E)
2
-40
-7
). Some LSB’s are zero
). In typical applications,
-1
to 2
-32
-26
-32
. With
. The loop
. Together
(EQ. 11)