hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 28

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-
forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.
NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-
forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.
1
2
3
4
5
Load the Write Address Register with 29
Enable Carrier Loop Filter Lag Accumulator holding register for reading.
Select the MSByte of the output holding register for output.
Assert RD low to output data on C0-7. (Must wait for 6 CLKs after loading the holding registers).
Select other bytes of holding register by changing A0-2 and asserting RD.
A0-2
C0-7
CLK
WR
RD
A0-2
C0-7
CLK
WR
RD
LOAD OUTPUT
HOLDING REG
4
1
29
0
1
3-28
2
HOLDING
ENABLE
READ
REG
FOR
3
FIGURE 22. LOOP FILTER ACCUMULATOR READ SEQUENCE
2
5
0
1
FIGURE 21. CONTROL REGISTER LOADING SEQUENCE
4
dec
6 CLKs
WAIT
to load the output holding registers.
5
DON’T CARE
6
ASSERT
2
DELAY
RD
TO
3 4
HSP50210
MSB
READ
3
3
EARLIEST TIME ANOTHER
5
READ
LOAD CAN BEGIN
2
4
1
2
DON’T CARE
3
READ
1
ADDRESS IS ASYNCHRONOUS TO CLK
4
0
READ
LSB
0
DATA IS
ASYNCHRONOUS
TO CLK
1