hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 11

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

AGC GAIN = (1.0 + M) x 2
The AGC Loop Filter integrates the scaled error signal to
provide a correction control term to the multipliers in the I and
Q path. The loop filter accumulator has internal upper and
lower limiters. The upper eight bits of the accumulator output
map to an exponent and mantissa format that is used to set
these upper and lower limits. The format, illustrated in Figure
8, is used for the AGC Upper Limit, AGC Lower Limit and the
Correction Control Term (AGC output). This format should not
be confused with the similar format used for the AGC Loop
Gain. The input to the AGC Loop Filter is included in Figure 8
to show the relative weighting of the input to output of the loop
filter. The loop filter input is represented as the eleven letter
“G”s. Lower case “e” and “m” detail the format for the AGC
Upper and Lower Limits. This change in type case should help
keep the AGC Limits and AGC Gain formats from being
confused. The AGC Upper and Lower Limits are set in the
AGC Loop Parameters Control Register, bits 0-15, (see Table
16). This 6-bit unsigned mantissa format provides for an AGC
output control range from 0.0000 to 0.9844, with a resolution
of 0.015625. The 2-bit exponent format provides an AGC
output control range from 1 to 8. The decimal values for each
of the 64 binary mantissa values is detailed in Table 4, while
Table 5 details the decimal value for the 4 exponent values.
Q
I
READ
REG
G
ADJUST
GAIN
AGC
E
UPPER
2
e e .m m m m m m
R
G
E
LIMIT †
3-11
1
AGC
(0 TO 24dB)
2
1.0000 TO 15.8572 = G
0
.2
M
L
T
I
I
-1
AGC
LOWER
LIMIT †
2
AGC LOOP FILTER
-2
FIGURE 8. AGC
+
2
-3
M
0.000 TO 1.07297(2
L
T
I
I
2
-4
CART/POLAR INPUT SELECT†
MANTISSA †
(2
R
E
G
AGC LOOP
2
-7
FIGURE 7. AGC LOOP BLOCK DIAGRAM
-5
GAIN
TO 2
AGC
2
S
H
T
-6
F
I
-14
2
-7
OUTPUT
I&D FILTER
I&D FILTER
)
G G G
2
R
E
G
(0.000 TO 0.9375)
-8
-7
EXPONENT †
)
AGC LOOP
2
HSP50210
ENABLE AGC †
-9
GAIN
2
AND AGC LIMITS BIT WEIGHTING
-10
G
2
M
U
X
-11
“0”
2
G
The AGC Output is implemented in the multiplier according
to Equation 8.
where m and e are the binary values for mantissa and
exponent found in Tables 4 and 5.
NOTE:This format is identical to the format used to program the
AGC Upper and Lower Limits, but in this usage it is not a pro-
grammed value. It is a representation of the digital AGC output
number which is presented to the Gain Adjuster (multipliers) to
correct the gain of the I and Q data signals in the main data path.
These equations yield a composite (mantissa and
exponent) AGC output range of 0.0000 to 1.9844(2
is a logarithmic range from 0 to 24dB. Figure 9 has graphed
the results of Equation 8 for both the linear and logarithmic
equations. Figure 9 also has a linear estimate of the
logarithmic equation. This linear approximation will be used
in calculating the AGC response time.
Out
Out
-12
M
U
X
G
AGC linear
AGC dB
2
-13
GAIN
ERROR
2
G
1.0
CARTESIAN TO POLAR
–
–
-14
THRSHLD †
AGC ERROR DETECT
AGC THRSHLD †
POWER
G
2
=
-15
COMPARE
TAN
G
20 log
=
+
G
2
=
I
-16
2
-1
-
1.0
+Q
1.64
---------- -
( )
2
Q
† Indicates a microprocessor control signal.
G
I
2
2
-17
+
1.0
m
G
2
AGC
0.8
-18
+
R
E
G
m
AGC
2
dcloutlvl
where dcloutlvl is the
magnitude output expressed
in dB from Full Scale (dBFS)
e
THRESH
MAGNITUDE
(0 - 1.1455)
PHASE
2
e
=
agc thresh
3
(EQ. 8A)
(EQ. 8B)
) which
1.64
----------- -
2