hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 37

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

POSITION
POSITION
POSITION
POSITION
31-24
23-18
17-14
31-0
31-0
BIT
BIT
BIT
BIT
7-3
8
2
1
0
Single/Double Rail
Sampling Error
Sampling Error
Accumulation
Lead Sampling Error
Enable
Lag Sampling Error
Enable
Invert Sampling Error
Symbol Tracking
Loop Filter Upper
Limit
Symbol Tracking
Loop Filter Lower
Limit
Not Used
Reserved
Symbol Tracking
Lead Gain Mantissa
(Acquisition)
FUNCTION
FUNCTION
FUNCTION
FUNCTION
TABLE 28. SYMBOL TRACKING LOOP CONFIGURATION CONTROL REGISTER (Continued)
TABLE 30. SYMBOL TRACKING LOOP FILTER LOWER LIMIT CONTROL REGISTER
TABLE 29. SYMBOL TRACKING LOOP FILTER UPPER LIMIT CONTROL REGISTER
TABLE 31. SYMBOL TRACKING LOOP FILTER GAIN (ACQ) CONTROL REGISTER
3-37
This bit sets whether sampling error is derived from symbol transitions on just the I rail (single rail) or both
the I&Q rails (dual rail). In single rail operation sampling error from the Q rail is nulled and only the I rail is
used. In dual rail operation the sampling error from both the I an Q rails is summed and then scaled by one
half.
0 = Dual Rail Operation.
1 = Single Rail Operation.
Note: Set to 1 for BPSK operation and 0 for QPSK operation.
These bits set the number of sampling error measurements to accumulate before running the Symbol Loop
Filter. The loop filter requires 8 CLKs to compute an output. The sampling error detector generates error
terms at the symbol rate. Thus, the error accumulator must be used if the symbol rate exceeds 1/8 CLK to
ensure that no error terms are missed (see Sampling Error Detector Section). The 5-bit value programmed
here is set to one less than the desired number of error terms to accumulate. For example, setting these
bits to 00011 (BINARY) would cause 4 error terms to be accumulated. A total range from 1 to 32 is provided.
0 = Sampling error enabled to lead path of loop filter.
1 = Sampling error to lead path of loop filter zeroed.
0 = Sampling error enabled to lag path of loop filter.
1 = Sampling error to lag path of loop filter zeroed (First Order Loop).
0 = Sampling error normal.
1 = Sampling error inverted.
The 32-bit two’s complement value programmed here sets the upper tracking limit of the Symbol Tracking Loop
Filter by setting the upper limit of the loop filter’s lag accumulator. If the limit is exceeded, the upper 32 bits of the
40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.
The 32-bit two’s complement value programmed here sets the Lower tracking limit of the Symbol Tracking Loop
Filter by setting the lower limit of the loop filter’s lag accumulator. If the running sum falls below the limit, the upper
32 bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.
No programming required.
Reserved. Set to 0 for proper operation.
These bits are the 4 fractional bits of the lead gain mantissa shown below:
Symbol Tracking Lead Gain Mantissa = 01. 2
This format provides a mantissa range from 1.0 to 1.9375 for mantissa settings from 0000 to 1111 Binary.
Bit position 17 is the MSB.
DESTINATION ADDRESS = 14
DESTINATION ADDRESS = 15
DESTINATION ADDRESS = 16
DESTINATION ADDRESS = 17
HSP50210
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
-1
2
-2
2
-3
2
-4.