ox16c954 ETC-unknow, ox16c954 Datasheet - Page 41

• Manufacturer Part Number: ox16c954
• Description: High Performance Quad Uart With 128-byte Fifos Intel / Motorola Bus Interface
• Manufacturer: ETC-unknow

NMR[4]: Bit 9 of Special Character 3
NMR[5]: Bit 9 of Special Character 4
NMR[7:6]: Reserved
NMR[0]: 9-bit mode enable
logic 0
logic 1
NMR[1]: Enable interrupt when 9
logic 0
logic 1
Special Character Detection
While the UART is in both 9-bit mode and Enhanced mode,
setting IER[5] will enable detection of up to four ‘address’
characters. The least significant eight bits of these four
programmable characters are stored in special characters
1 to 4 (XON1, XON2, XOFF1 and XOFF2 in 650 mode)
registers and the 9
programmed in NMR[5] to NMR[2] respectively.
NMR[2]: Bit 9 of Special Character 1
NMR[3]: Bit 9 of Special Character 2
Bits 6 and 7 of NMR are always cleared and reserved for
future use.
15.10 Modem Disable Mask ‘MDM’
The MDM register is located at offset 0x0E of the ICR
This register is cleared after a hardware reset to maintain
compatibility with 16C550. It allows the user to mask
interrupts, sleep operation due to individual modem lines or
the serial input line.
MDM[0]: Disable delta CTS
logic 0
logic 1
MDM[1]: Disable delta DSR
logic 0
logic 1
Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
9-bit mode is disabled.
9-bit mode is enabled.
Receiver interrupt for detection of an ‘address’
character (i.e. 9
Receiver interrupt for detection of an ‘address’
character (i.e. 9
1 interrupt is asserted.
Delta CTS is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta CTS
can wake up the UART when it is asleep under
auto-sleep operation.
interrupt or wake up the UART.
Delta DSR is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta DSR
can wake up the UART when it is asleep under
auto-sleep operation.
interrupt or wake up the UART.
Delta CTS is disabled. It can not generate an
Delta DSR is disabled. It can not generate an
th
bit of these characters are
th
th
bit set) is disabled.
bit set) is enabled and a level
th
bit is set
MDM[2]: Disable Trailing edge RI
logic 0
logic 1
MDM[3]: Disable delta DCD
logic 0
logic 1
MDM[7:4]: Reserved
These bits must be set to ‘0000’
15.11 Readable FCR ‘RFC’
The RFC register is located at offset 0x0F of the ICR
This read-only register returns the current state of the FCR
register (Note that FCR is write-only). This register is
included for diagnostic purposes.
15.12 Good-data status register ‘GDS’
The GDS register is located at offset 0x10 of the ICR
Good data status is set when the following conditions are
true:
GDS[0]: Good Data Status
GDS[7:1]: Reserved
ISR reads level0 (no interrupt), level 2 or 2a
(receiver data) or level 3 (THR empty) interrupt.
LSR[7] is clear i.e. no parity error, framing error
or break in the fifo.
LSR[1] is clear i.e. no overrun error has occurred.
Trailing edge RI is enabled. It can generate a
level 4 interrupt when enabled by IER[3].
Trailing edge RI can wake up the UART when it
is asleep under auto-sleep operation.
generate an interrupt or wake up the UART.
Delta DCD is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta DCD
can wake up the UART when it is asleep under
auto-sleep operation.
interrupt or wake up the UART.
Trailing edge RI is disabled. It can not
Delta DCD is disabled. It can not generate an
OX16C954 rev B
Page 41