ox16c954 ETC-unknow, ox16c954 Datasheet - Page 25

• Manufacturer Part Number: ox16c954
• Description: High Performance Quad Uart With 128-byte Fifos Intel / Motorola Bus Interface
• Manufacturer: ETC-unknow

LCR[1:0]: Data length
LCR[1:0] Determines the data length of serial characters.
Note however, that these values are ignored in 9-bit data
framing mode, i.e. when NMR[0] is set.
LCR[2]: Number of stop bits
LCR[2] defines the number of stop bits per serial character.
LCR[5:3]: Parity type
The selected parity type will be generated during
transmission and checked by the receiver, which may
produce a parity error as a result. In 9-bit mode parity is
disabled and LCR[5:3] is ignored.
LCR[6]: Transmission break
logic 0
logic 1
It is the responsibility of the software driver to ensure that
the break duration is longer than the character period for it
to be recognised remotely as a break rather than data.
LCR[7]: Divisor latch enable
logic 0
logic 1
Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
Table 12: LCR Stop Bit Number Configuration
Table 11: LCR Data Length Configuration
LCR[1:0]
LCR[5:3]
LCR[2]
Table 13: LCR Parity Configuration
001
011
101
111
xx0
00
01
10
11
Break transmission disabled.
Forces the transmitter data output SOUT low
to alert the communication terminal, or send
zeros in IrDA mode.
Access to DLL and DLM registers disabled.
Access to DLL and DLM registers enabled.
0
1
1
Data length
5,6,7,8
6,7,8
Parity bit forced to 1
Parity bit forced to 0
5
Even parity bit
Odd parity bit
Data length
No parity bit
Parity type
5 bits
6 bits
7 bits
8 bits
No. stop
bits
1.5
1
2
9.3
This register provides the status of data transfer to CPU.
LSR[0]: RHR data available
logic 0
logic 1
LSR[1]: RHR overrun error
logic 0
logic 1
LSR[2]: Received data parity error
logic 0
logic 1
The flag will be set when the data item in error is at the top
of the RHR and cleared following a read of the LSR. In 9-
bit mode LSR[2] is no longer a flag and corresponds to the
9
LSR[3]: Received data framing error
logic 0
logic 1
This status bit is set and cleared in the same manner as
LSR[2]. When a framing error occurs, the UART will try to
re-synchronise by assuming that the error was due to
sampling the start bit of the next data item.
LSR[4]: Received break error
logic 0
logic 1
A break condition occurs when the SIN line goes low
(normally signifying a start bit) and stays low throughout
the start, data, parity and first stop bit. (Note that the SIN
line is sampled at the bit rate). One zero character with
associated break flag set will be transferred to the RHR
and the receiver will then wait until the SIN line returns
high. The LSR[4] break flag will be set when this data item
gets to the top of the RHR and it is cleared following a read
of the LSR.
LSR[5]: THR empty
logic 0
logic 1
th
bit of the received data in RHR.
Line Status Register ‘LSR’
RHR is empty: no data available
RHR is not empty: data is available to be read.
No overrun error.
Data was received when the RHR was full. An
overrun error has occurred. The error is flagged
when the data would normally have been
transferred to the RHR.
No parity error in normal mode or 9
received data is ‘0’ in 9-bit mode.
Data has been received that did not have
correct parity in normal mode or 9
received data is ‘1’ in 9-bit mode.
No framing error.
Data has been received with an invalid stop bit.
No receiver break error.
The receiver received a break.
Transmitter FIFO (THR) is not empty.
Transmitter FIFO (THR) is empty.
OX16C954 rev B
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