ox16c954 ETC-unknow, ox16c954 Datasheet - Page 10

• Manufacturer Part Number: ox16c954
• Description: High Performance Quad Uart With 128-byte Fifos Intel / Motorola Bus Interface
• Manufacturer: ETC-unknow

4
Please refer to Section 3 for actual Signal Name to Pin Number assignments, for the selected package.
Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
TQFP
Clock
50
51
45
Processor Interface Pins in Intel Mode (I/M# = ‘1’)
53
73
68
33
28
46 to 48
15 to 11
9 to 7
31
70
Processor Interface Pins in Motorola Mode (I/M# = ‘0’)
53
28
70
73
68
33
46 to 48
P
IN
D
ESCRIPTIONS
PLCC
35
36
30
37
54
50
20
16
32 to 34
5 to 1
68 to 66
18
52
37
16
52
54
50
20
32 to 34
Dir
I
O
I
I
I
I
I
I
I
I/O
I
I
I
I
I
I
I
I
I
1
Name
XTLI
XTLO
CLKSEL
RESET
CS[3]#
CS[2]#
CS[1]#
CS[0]#
A[2:0]
DB[7:0]
IOW#
IOR#
RESET#
DS#
UNUSED
A4
A3
A[2:0]
Description
Crystal oscillator input or external clock pin, for the UART channels.
Crystal oscillator frequency maximum 60MHz
Crystal oscillator output.
Not used when an alternative TTL level clock is applied to XTLI and can
be left unconnected
This pin is provided to select an internal clock prescaler on power up. In
16C554 devices this pin is a VDD. When CLKSEL pin is high the internal
prescaler is bypassed (a 1.8432MHz clock is assumed). Connect this pin
to GND to enable the internal clock prescaler. The complement of this pin
is loaded in bit 7 of the MCR register after a hardware reset.
This pin can also be used as an alternative external clock pin under
software control (replacing XTLI and thus reducing noise/power due to
XTLO) for embedded applications.
Active-high Hardware Reset. The configuration of OX16C954 after a
hardware reset is described in section 7.1. This pin exhibits a small
hysteresis to provide noise immunity. This pin must be tied inactive when
not in use.
Active-low Chip-Selects for each Uart channel, in Intel bus mode.
CS3# - Chip select for Uart 3
CS2# - Chip select for Uart 2
CS1# - Chip select for Uart 1
CS0# - Chip select for Uart 0
Address lines to select the Uart (channel) registers.
Eight-bit 3-state data bus.
Active-low write strobe in Intel bus mode.
Active-low read strobe in Intel bus mode.
Active-low Hardware Reset. The configuration of OX16C954 after a
hardware reset is described in section 7.1. This pin exhibits a small
hysteresis to provide noise immunity. This pin must be tied inactive when
not in use.
Active-low Data-Strobe.
(In Motorola bus mode, individual registers are accessed using DS#,
R/W# and A[4:0])
In Motorola bus mode these pins are unused and must be connected to
VDD or GND.
The A[4:3] combination selects individual channels as follows:
Address lines to select the UART (channel) registers.
00 = UART 0 selected
01 = UART 1 selected
10 = UART 2 selected
11 = UART 3 selected
OX16C954 rev B
Page 10