ox16c954 ETC-unknow, ox16c954 Datasheet - Page 23

• Manufacturer Part Number: ox16c954
• Description: High Performance Quad Uart With 128-byte Fifos Intel / Motorola Bus Interface
• Manufacturer: ETC-unknow

8
Both the transmitter and receiver have associated holding
registers (FIFOs), referred to as the transmitter holding
register (THR) and receiver holding register (RHR)
respectively.
In normal operation, when the transmitter finishes
transmitting a byte it will remove the next data from the top
of the THR and proceed to transmit it. If the THR is empty,
it will wait until data is written into it. If THR is empty and
the last character being transmitted has been completed
(i.e. the transmitter shift register is empty) the transmitter is
said to be idle. Similarly, when the receiver finishes
receiving a byte, it will transfer it to the bottom of the RHR.
If the RHR is full, an overrun condition will occur (see
section 9.3).
Data is written into the bottom of the THR queue and read
from the top of the RHR queue completely asynchronously
to the operation of the transmitter and receiver.
The size of the FIFOs is dependent on the setting of the
FCR register. When in Byte mode, these FIFOs only
accept one byte at a time before indicating that they are
full; this is compatible with the 16C450. When in a FIFO
mode, the size of the FIFOs is either 16 (compatible with
the 16C550) or 128.
Data written to the THR when it is full is lost. Data read
from the RHR when it is empty is invalid. The empty or full
status of the FIFOs are indicated in the Line Status
Register ‘LSR’ (see section 9.3). Interrupts are generated
when the UART is ready for data transfer to/from the
FIFOs. The number of items in each FIFO may also be
read back from the transmitter FIFO level (TFL) and
receiver FIFO level (RFL) registers (see section 15.2).
8.1
FCR[0]: Enable FIFO mode
logic 0
logic 1
This bit should be enabled before setting the FIFO trigger
levels.
FCR[1]: Flush RHR
logic 0
logic 1
This is only operative when already in a FIFO mode. The
RHR is automatically flushed whenever changing between
Byte mode and a FIFO mode. This bit will return to zero
after clearing the FIFOs.
Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
T
RANSMITTER AND RECEIVER
FIFO Control Register ‘FCR’
Byte mode.
FIFO mode.
No change.
Flushes the contents of the RHR
FIFO
S
FCR[2]: Flush THR
logic 0
logic 1
manner as FCR[1] does for the RHR.
DMA Transfer Signalling:
FCR[3]: DMA signalling mode / Tx trigger level enable
logic 0
logic 1
Note: In DMA mode 0, the transmitter trigger level is
DMA Control signals can be generated using the TXRDY#
and RXRDY# pins. Their operation is defined as follows:
The TXRDY# pin has no hysteresis and is simply activated
using a comparison operation. When the UART is in DMA
mode 0 (or in Byte mode), the TXRDY# output pin is active
(low) whenever any channels transmit FIFO (THR) is
empty, otherwise it is inactive.
When in DMA mode 1, the TXRDY# pin is inactive (high)
when every channels transmit FIFO is full, otherwise it is
active, signifying that one or more channels have room in
their transmit FIFOs.
The RXRDY# pin can operate with hysteresis. In DMA
mode 0 (or in Byte mode), RXRDY# is only active (low)
when one or more channels have data in their receiver
FIFO. It is inactive therefore, when all channels receiver
FIFOs are empty.
When in DMA mode 1, RXRDY# operates as follows:
1.
2.
Note for the 80 pin TQFP package, individual channel
TXRDY#, RXRDY# signals are also generated.
FCR[5:4]: THR trigger level
Generally in 450, 550, extended 550 and 950 modes these
bits are unused (see section 5 for mode definition). In 650
mode they define the transmitter interrupt trigger levels and
in 750 mode FCR[5] increase the FIFO size.
RXRDY# is set active when any channels receiver
FIFO fill level has reached the receiver interrupt
trigger level for that channel, or a time-out event has
occurred (see section 10.3). It remains active until
condition 2 (defined below) is met.
RXRDY# is set inactive when every channels receiver
has been emptied. It remains in this state until
condition 1 (defined above) occurs again.
ALWAYS set to 1, thus ignoring FCR[5:4] and TTL.
Flushes the contents of the THR, in the same
No change.
DMA mode '0'.
DMA mode '1'.
OX16C954 rev B
Page 23