ox16c954 ETC-unknow, ox16c954 Datasheet - Page 16

• Manufacturer Part Number: ox16c954
• Description: High Performance Quad Uart With 128-byte Fifos Intel / Motorola Bus Interface
• Manufacturer: ETC-unknow

would result in a 550 compatible device with 16 byte deep
FIFOs.
5
The OX16C954 device is a four-channel device backward compatible with the 16C454, 16C554, 16C654 and 16C750 UARTs.
Each of the four channels are identical and independent in terms of functionality, with the exception of some shared pins (for
example, CLKSEL, FIFOSEL#, CLK and RESET). The remainder of this document therefore discusses the operation of a single
channel only.
The operation of each Uart Channel depends on a number of mode settings, which are referred to throughout this section. The
modes, conditions and corresponding FIFO depth are tabulated below:
Note 1: 950 mode configuration is identical to 650 configuration
5.1
After a hardware reset, bit 0 of the FIFO Control Register
(‘FCR’) is cleared, hence the UART is compatible with the
16C450. The transmitter and receiver FIFOs (referred to as
the ‘Transmit Holding Register’ and ‘Receiver Holding
Register’ respectively) have a depth of one. This is referred
to as ‘Byte mode’. When FCR[0] is cleared, all other mode
selection parameters are ignored.
5.2
Connect FIFOSEL# to VDD. After a hardware reset, writing
a 1 to FCR[0] will increase the FIFO size to 16, providing
compatibility with 16C550 devices. Since this pin is VDD in
16C554 devices, replacing a 16C554 with OX16C954
5.3
Connect FIFOSEL# to GND. Writing a 1 to FCR[0] will now
increase the FIFO size to 128, thus providing a 550 device
with 128 deep FIFOs.
5.4
Writing a 1 to FCR[0] will increase the FIFO size to 16. In a
similar fashion to 16C750, the FIFO size can be further
increased to 128 by writing a 1 to FCR[5]. Note that access
to FCR[5] is protected by LCR[7]. i.e., to set FCR[5],
Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
M
450 Mode
550 Mode
Extended 550 Mode
750 Mode
ODE
Extended 550
UART Mode
S
950
450
550
650
750
ELECTION
1
FIFO
size
128
128
128
128
16
1
FCR[0]
0
1
1
1
1
1
Table 3: UART Mode Configuration
Enhanced mode
(EFR[4]=1)
X
0
0
1
0
1
software should first set LCR[7] to temporarily remove the
guard. Once FCR[5] is set, the software should clear
LCR[7] for normal operation.
The 16C750 additional features are available as long as
the UART is not put into Enhanced mode; i.e. ensure
EFR[4] = ‘0’. These features are:
5.5
The OX16C954 UART is compatible with the 16C650 when
EFR[4] is set, i.e. the device is in Enhanced mode. As 650
software drivers usually put the device in Enhanced mode,
running 650 drivers on the one of the UART channels will
result in 650 compatibility with 128 deep FIFOs, as long as
FCR[0] is set. Note that the 650 emulation mode of the
OX16C954 provides 128-deep FIFOs whereas the
standard 16C650 has only 32 byte FIFOs.
650 mode has the same enhancements as the 16C750
over the 16C550, but these are enabled using different
registers.
There are also additional enhancements over those of the
16C750 in this mode. These are -
1.
2.
(guarded with LCR[7] = 1)
Deeper FIFOs
Automatic RTS/CTS out-of-band flow control
Sleep mode
Automatic in-band flow control
Special character detection
650 Mode
FCR[5]
X
0
X
X
1
X
FIFOSEL#
OX16C954 rev B
Pin
X
X
X
1
0
1
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