isppac10 Lattice Semiconductor Corp., isppac10 Datasheet - Page 8

• Manufacturer Part Number: isppac10
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 8. I/O Cell
sysIO Capability
The ispMACH 5000VG devices are divided into four sysIO banks, where each bank is capable of supporting 14 dif-
ferent I/O standards. Each sysIO bank has its own I/O supply voltage (V
resources allowing each bank complete independence from the others. Each I/O within a bank is individually con-
figurable based on the V
V
Table 2. ispMACH 5000VG Supported I/O Standards
LVTTL
LVCMOS-3.3
LVCMOS-2.5
LVCMOS-1.8
PCI 3.3
PCI-X
AGP-1X
SSTL3, Class I & II
SSTL2, Class I & II
CTT 3.3
CTT 2.5
HSTL, Class I
HSTL, Class III
GTL+
LVPECL, Differential
LVDS
1. LVDS and LVPECL are only supported on the dedicated clock pins.
REF
and V
1
sysIO Standard
TT
Shared (Segment) PTOE 0
Shared (Segment) PTOE 1
Shared (Segment) PTOE 2
Shared (Segment) PTOE 3
.
1
from Macrocell
Data Output
CCO
GOE0
GOE1
PTOE
and V
TOE
REF
settings. Table 2 lists the sysIO standards with the typical values for V
Data Input to Macrocell
V
3.3V
3.3V
2.5V
1.8V
3.3V
3.3V
3.3V
3.3V
2.5V
3.3V
2.5V
1.5V
1.5V
N/A
N/A
N/A
Data Input to Routing
CCO
(V
8
open drain outputs)
CCO
Output Buffer
independent for
V
other I/Os
CCO
in bank
ispMACH 5000VG Family Data Sheet
to all
(V
1.25V
1.25V
0.75V
V
1.5V
1.5V
0.9V
1.0V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
REF
REF
V
Input Buffer
CMOS/TTL
Input Buffer
REF
independent)
dependent
CCO
+
–
) and reference voltage (V
this bank
V
GND
CCO
V
other I/Os in bank
REF
for
to all
1.25V
1.25V
0.75V
1.5V
1.5V
1.5V
1.5V
V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Pad
I/O
TT
CCO
REF
)
,