isppac10 Lattice Semiconductor Corp., isppac10 Datasheet - Page 11

• Manufacturer Part Number: isppac10
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
IEEE 1149.1-Compliant Boundary Scan Testability
All ispMACH 5000VG devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This
allows functional testing of the circuit board on which the device is mounted through a serial scan path that can
access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded
directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices
can be linked into a board-level serial scan path for more board-level testing. The test access port has its own sup-
ply voltage and can operate with LVCMOS3.3, 2.5 and 1.8V standards.
sysIO Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispMACH 5000VG family of devices
allows this by offering the user the ability to quickly configure the physical nature of the sysIO cells. This quick con-
figuration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lat-
tice's ispVM™ System programming software can either perform the quick configuration through the PC parallel
port, or can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
In-system programming of devices provides a number of significant benefits including rapid prototyping, lower
inventory levels, higher quality and the ability to make in-field modifications. All ispMACH 5000VG devices provide
TM
In-System Programming (ISP
) capability through their Boundary Scan Test Access Port. This capability has been
implemented in a manner that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE
1532 as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-
defined interface.
The ispMACH 5000VG devices can be programmed across the commercial temperature and voltage range. The
PC-based Lattice software facilitates in-system programming of ispMACH 5000VG devices. The software takes the
JEDEC file output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto-
mated test equipment. This equipment can then be used to program ispMACH 5000VG devices during the testing
of a circuit board.
Security Bit
A programmable security bit is provided on the ispMACH 5000VG devices as a deterrent to unauthorized copying
of the array configuration patterns. Once programmed, this bit prevents readback of the programmed pattern by a
device programmer, securing proprietary design from competitors. The security bit also prevents programming and
verification. The entire device must be erased in order to erase the security bit.
Hot Socketing
The ispMACH 5000VG devices are well suited for those applications that require hot socketing capability. Hot sock-
eting a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs with-
out being damaged. Additionally, it requires that the effects of the powered-down device be minimal on active
signals.
Density Migration
The ispMACH 5000 family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-
geted for a high density device to a lower density device. However, the exact details of the final resource utilization
will impact the likely success in each case.
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