isppac10 Lattice Semiconductor Corp., isppac10 Datasheet - Page 27

• Manufacturer Part Number: isppac10
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
sysCLOCK PLL Timing
Boundary Scan Timing Specifications
t
t
t
t
f
f
f
f
t
t
t
t
t
t
t
t
t
t
1. This condition assures that the output phase jitter (t
2. Accumulated jitter measured over 10,000 waveform samples.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
BTCP
BTCH
BTCL
BTSU
BTH
BRF
BTCO
BTOZ
BTVO
BVTCPSU
BTCPH
BTUCO
BTUOZ
BTUOV
R
INSTB
PWH
PWL
MDIVIN
MDIVOUT
VDIVIN
VDIVOUT
OUTDUTY
JIT(CC)
JIT(φ)
CLK_OUT_DLY
φ
LOCK
PLL_DELAY
RANGE
PLL_RSTR
PLL_RSTW
,t
Symbol
Symbol
F
TCK [BSCAN test] clock cycle
TCK [BSCAN test] pulse width high
TCK [BSCAN test] pulse width low
TCK [BSCAN test] setup time
TCK [BSCAN test] hold time
TCK [BSCAN test] rise and fall time
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to data output disable
TAP controller falling edge of clock to data output enable
BSCAN test Capture register setup time
BSCAN test Capture register hold time
BSCAN test Update reg, falling edge of clock to valid output
BSCAN test Update reg, falling edge of clock to output disable
BSCAN test Update reg, falling edge of clock to output enable
Input clock, rise and fall time
Input clock stability, period jitter (peak)
Input clock, high time
Input clock, low time
M Divider input, frequency range
M Divider output, frequency range
V Divider input, frequency range
V Divider output, frequency range
Output clock, duty cycle
Output clock, cycle to cycle jitter (peak)
Output clock, accumulated phase jitter (peak)
Input clock to CLK_OUT delay
Input clock to external feedback delta
Time to acquire phase lock after input stable
Delay increment
Total output delay range
Reset recovery time of the M-divider
Minimum reset pulse width
Parameter
Over Recommended Operating Conditions
Parameter
JIT(φ)
) will remain within specification.
1
2
27
80MHz ≤ f
80MHz ≤ f
5MHz ≤ f
5MHz ≤ f
External feedback
Clean Reference,
Clean Reference,
Clean Reference,
Clean Reference,
Internal feedback
20% to 80%
ispMACH 5000VG Family Data Sheet
Conditions
MDIVOUT
MDIVOUT
MDIVOUT
MDIVOUT
—
—
—
—
—
—
—
—
—
—
—
—
—
< 80MHz
≤ 180MHz
< 80MHz
≤ 180MHz
1
Min.
40
20
20
10
50
10
—
—
—
—
—
—
8
8
+/- 0.35
+/- 2.45
11.0
Min
1.6
1.6
6.0
60
40
—
—
—
—
—
—
—
—
—
5
5
5
Max.
10
10
10
25
25
25
—
—
—
—
—
—
—
—
+/- 0.65
+/- 4.55
+/- 200
+/- 200
+/- 100
+/- 200
+/- 100
Max
180
180
200
180
500
3.0
60
30
—
—
—
—
1
mV/ns
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
ns
ps
ns
ns
ps
ps
ps
ps
ns
ps
µs
ns
ns
ns
ns
%