isppac10 Lattice Semiconductor Corp., isppac10 Datasheet - Page 18

• Manufacturer Part Number: isppac10
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Timing Model
The task of determining the timing through the ispMACH 5000VG family, like any CPLD, is relatively simple. The
timing model provided in Figure 11 shows the specific delay paths. Once the implementation of a given function is
determined either conceptually or from the software report file, the delay path of the function can easily be deter-
mined from the timing model. The Lattice design tools report the timing delays based on the same timing model for
a particular design. Note that the internal timing parameters are given for reference only, and are not tested. The
external timing parameters are tested and guaranteed for every device. For more information on the timing model
and usage, please refer to Technical Note TN1001: ispMACH 5000VG Timing Model Design and Usage Guidelines.
Figure 11. ispMACH 5000VG Timing Model
Italicized items are optional delay adders
SCLK
From Feedback
RST
OE
IN
t
GCLK_IN
t
t
t
t
t
RST
GOE
t
IOI
IOI
IOI
t
IOI
IN
t
PLL_SEC_DELAY
t
PLL_DELAY
t
t
GCLK
INREG
t
ROUTE
t
t
GRP
BLK
t
LP
t
t
t
t
PTCLK
t
t
PTSA
BCLK
PTSR
EXP
BSR
t
PDb
t
SPTOE
t
PTOE
18
Data
C.E.
S/R
MC Reg
t
PDi
ispMACH 5000VG Family Data Sheet
Q
t
t
t
t
t
FBK
BUF
IOO
DIS
EN
OUT
Feedback