isppac10 Lattice Semiconductor Corp., isppac10 Datasheet - Page 3

• Manufacturer Part Number: isppac10
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
The ispMACH5000VG devices also contain sysCLOCK Phase Locked Loops (PLLs) that provide designers with
increased clocking flexibility. The PLLs can be used to synthesize new clocks for use on-chip or elsewhere within
the system. They can also be used to deskew clocks, again both at the chip and system levels. A variable delay line
capability further improves this and allows designers to retard or advance the clock in order to tune set-up and
clock-to-out times for optimal results. The ispMACH 5000VG Family Selection Guide (Table 1) details the key
attributes and packages for the ispMACH 5000VG devices.
ispMACH 5000VG Architecture
The ispMACH 5000VG Family of In-System Programmable High Density Logic Devices is based on segments con-
taining four Generic Logic Blocks (GLBs) and a hierarchical routing pool (GRP) structure interconnecting the seg-
ments. A segment routing pool (SRP) connects each GLB in a segment allowing the maximum flexibility and
speed.
Outputs from the GLBs drive the Segment Routing Pool (SRP) and the Global Routing Pool (GRP). Enhanced
switching resources are provided to allow signals in the Segment Routing Pool to drive any or all the GLBs in the
segment. Optimal switching is provided to allow all signals in the Global Routing Pool to be routed to any or all
SRPs. This mechanism allows fast, efficient connections across the entire device.
Segment
Each segment contains four GLBs and a segment routing pool (SRP). Each GLB has 32 internal feedback outputs
and 16 external feedback outputs, for a total of 48 outputs from each GLB feeding the SRP. The SRP contains up to
384 signals, 48 from each GLB and 192 from the GRP, with full routing capability. This routing scheme maximizes
the flexibility and speed of the device without sacrificing the routing.
Figure 2. Segment
Generic Logic Block
Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms
and three control product terms. The GLB has 68 inputs from the Segment Routing Pool, which are available in
both true and complement form for every product term. The three control product terms are used for shared reset,
clock and output enable functions. Figure 3 shows the structure of the GLB from the macrocell perspective. This is
referred to as a macrocell slice. There are 32 macrocell slices per GLB.
AND-Array
The programmable AND-Array consists of 68 inputs and 163 output product terms. The 68 inputs from the SRP are
used to form 136 lines in the AND-Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 163 output product terms via a wired AND. Each of the 160 logic product terms feed the Dual-
OR Array with the remaining three control product terms feeding the Shared PT Clock, Shared PT Reset and
Shared PT OE. Every set of five product terms from the 160 logic product terms forms a product term cluster start-
Clocks
Clocks
4
4
GLB
GLB
GRP
GRP
To
To
48
48
48
48
68
68
Segment
Routing
(SRP)
Pool
From
GRP
192
3
68
68
48
48
ispMACH 5000VG Family Data Sheet
GLB
GLB
GRP
GRP
48
48
To
To
Clocks
Clocks
4
4