mm912f634 Freescale Semiconductor, Inc, mm912f634 Datasheet - Page 77

• Manufacturer Part Number: mm912f634
• Description: Mm912f634 - Integrated S12 Based Relay Driver With Lin
• Manufacturer: Freescale Semiconductor, Inc

Functional Description and Application Information
4.9
The MM912F634 analog die includes a configurable window watchdog, which is active in Normal mode. The watchdog module
is based on a separate clock source (f
(t
During Low Power mode, the watchdog feature is not active, a D2D read during Stop mode will have the WDOFF bit set.
To clear the watchdog counter, a alternating write must be performed to the Watchdog Service Register (WDSR). The first write
after the RESET_A has been released has to be 0xAA. The next one must be 0x55.
After the RESET_A has been released, there will be a standard (non-window) watchdog active with a fixed timeout of t
The Watchdog Window Open (WDWO) bit is set during that time and the window watchdog can be configured (WDR) without
changing the initial timeout, and can be trimmed using the trim value given in the MCU trimming Flash section. See
“MM912F634 - Analog Die
To enable the window watchdog, the initial counter reset has to be performed by writing 0xAA to the Watchdog Service Register
(WDSR) before t
If the t
will occur.
Once entering Window Watchdog mode, the first half of the time t
an alternating write of 0x55 and 0xAA must be performed within the second half of the t
indicate the current status of the window. A timeout or wrong value written to the WDSR will force a watchdog reset.
For debug purpose, the watchdog can be completely disabled by applying V
watchdog will be disabled as long as V
indicate the watchdog being disabled. The WDSR register will reset to default once the watchdog is disabled. Once the watchdog
is re-enabled, the initial watchdog sequence has to be performed.
During Low Power mode, the Watchdog clock is halted and the Watchdog Service Register (WDSR) is reset to the default state.
Freescale Semiconductor
WDTO
IWDTO
) can be configured between 10 ms and 1280 ms (typ.) using the Watchdog Register (WDR).
Window Watchdog
timeout is reached with no counter reset or a value different from 0xAA was written to the WDSR, a watchdog reset
IWDTO
Standard Initial Watch Dog (no window)
is reached.
Trimming".
Initial WD Reg.
WRITE = 0xAA
t
IWDTO
Figure 21. MM912F634 Analog Die Watchdog Operation
BASE
TST
) operating independent from the MCU based D2DCLK clock. The watchdog timeout
is present. The watchdog is guaranteed functional for V
Window Watch Dog
Window Closed
t
WDTO
Window WD timing (t
/ 2
WRITE = 0x55
WD Register
Window Watch Dog
WDTO
Window Open
WDTO
t
WDTO
)
forbids a counter reset. To reset the watchdog counter,
/ 2
Window Watch Dog
Window Closed
TST
to the TCLK pin while TEST_A is grounded. The
WDTO
Window Watch Dog
. A Window Open (WDWO) flag will
Window Open
(to be continued)
WRITE = 0xAA
WD Register
TSTEN
. The WDOFF bit will
Window Watchdog
t
Section 4.25,
MM912F634
IWDTO
.
77