mm912f634 Freescale Semiconductor, Inc, mm912f634 Datasheet - Page 179

• Manufacturer Part Number: mm912f634
• Description: Mm912f634 - Integrated S12 Based Relay Driver With Lin
• Manufacturer: Freescale Semiconductor, Inc

Functional Description and Application Information
4.28.2.2.4
Read: Anytime.
Write: Anytime.
The IFRON bit of the MMCCTL1 register is used to make program IFR sector visible in the memory map.
Table 246. MODE Field Descriptions
4.28.3
The MMC block performs several basic functions of the S12S sub-system operation: MCU operation modes, priority control,
address mapping, select signal generation, and access limitations for the system. Each aspect is described in the following
subsections.
4.28.3.1
4.28.3.2
4.28.3.2.1
The BDM firmware lookup tables and BDM register memory locations share addresses with other modules. However, they are
not visible in the memory map during user’s code execution. The BDM memory resources are enabled only during the READ_BD
and WRITE_BD access cycles to distinguish between accesses to the BDM memory area and accesses to the other modules.
(Refer to BDM Block Guide for further details).
When the MCU enters active BDM mode, the BDM firmware lookup tables and the BDM registers become visible in the local
memory map in the range 0xFF00-0xFFFF (global address 0x3_FF00 - 0x3_FFFF) and the CPU begins execution of firmware
commands or the BDM begins execution of hardware commands. The resources which share memory space with the BDM
module will not be visible in the memory map during active BDM mode.
Freescale Semiconductor
Address: 0x0033
Reset
W
R
IFRON
•
•
Field
0
Normal single-chip mode
There is no external bus in this mode. The MCU program is executed from the internal memory and no external
accesses are allowed.
Special single-chip mode
This mode is generally used for debugging single-chip operation, boot-strapping or security related operations. The
active background debug mode is in control of the CPU code execution and the BDM firmware is waiting for serial
commands sent through the BKGD pin. There is no external bus in this mode.
Functional Description
Program IFR visible in the memory map
Write: Anytime
This bit is used to make the IFR sector of the Program Flash visible in the global memory map.
0 Not visible in the global memory map.
1 Visible in the global memory map in the range (See
MCU Operating Mode
Memory Map Scheme
0
0
7
MMC Control Register (MMCCTL1)
CPU and BDM Memory Map Scheme
[0x0_0400 - 0x0_047F]: IFR contents
0
0
6
Figure 52. MMC Control Register (MMCCTL1)
5
0
0
0
0
4
Figure
Description
44):
0
0
3
Memory Mapping Control (S12SMMCV1)
0
0
2
1
0
0
MM912F634
IFRON
0
0
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