mm912f634 Freescale Semiconductor, Inc, mm912f634 Datasheet - Page 309

• Manufacturer Part Number: mm912f634
• Description: Mm912f634 - Integrated S12 Based Relay Driver With Lin
• Manufacturer: Freescale Semiconductor, Inc

Functional Description and Application Information
4.38
4.38.1
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can
poll the SPI status flags or the SPI operation can be interrupt driven.
4.38.1.1
SPI — Serial Peripheral Interface
SS — Slave Select
SCK — Serial Clock
MOSI — Master Output, Slave Input
MISO — Master Input, Slave Output
MOMI — Master Output, Master Input
SISO — Slave Input, Slave Output
4.38.1.2
The S12SPIV4 includes these distinctive features:
4.38.1.3
The SPI functions in three modes: run, wait, and stop.
This is a high level description only, detailed descriptions of operating modes are contained in
Mode
Freescale Semiconductor
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Master mode and slave mode
Bi-directional mode
Slave select output
Mode fault error flag with CPU interrupt capability
Double-buffered data register
Serial clock with programmable polarity and phase
Control of SPI operation during wait mode
Run mode
This is the basic mode of operation.
Wait mode
SPI operation in wait mode is a configurable low-power mode, controlled by the SPISWAI bit located in the SPICR2
register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode. If the SPISWAI bit is set, the SPI
goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any
transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave,
reception and transmission of a byte continues, so that the slave stays synchronized to the master.
Stop mode
The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission
in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays synchronized to the master.
Serial Peripheral Interface (S12SPIV4)
Introduction
Glossary of Terms
Features
Modes of Operation
Serial Peripheral Interface (S12SPIV4)
Section 4.38.4.7, “Low Power
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