mm912f634 Freescale Semiconductor, Inc, mm912f634 Datasheet - Page 146

• Manufacturer Part Number: mm912f634
• Description: Mm912f634 - Integrated S12 Based Relay Driver With Lin
• Manufacturer: Freescale Semiconductor, Inc

Functional Description and Application Information
4.19.5.3
The conversion timing is based on the ADCCLK generated by the ADC prescaler (PS) out of the D2DCLK signal. The prescaler
needs to be configured to have the ADCCLK match the specified f
A conversion is divided into the following 27+ clock cycles:
12c (count up to Ch10) + 9c (sample) + 18c (conversion) = 39 cycles from start to end of conversion.
1c (count) + 9c (sample Ch15) + 18c (conversion Ch15) + 4c (in between) + 0c (count further to Ch10 is performed while
converting ch15) + 9c (sample) + 18c (conversion) = 59 cycles from start to end of both conversions.
Freescale Semiconductor
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9 cycle sampling time
18 cycle remaining conversion time
A worst case (only channel 14) of 15 clock cycles to count up to the selected channel (15, 0, 1,....14)
4 cycles between two channels
Example 2. Sequence of Channel 10 (VSENSE) + Channel 15 (Offset Compensation)
Conversion Timing
Example 1. Single Conversion Channel 10 (VSENSE)
Figure 38. Automatic Offset Compensation
ACCR – ADC Conversion Control Register
OCE – Offset Compensation Enable = 1
MCU – IFR (4C..4F) => CTR0..3
Offset is calculated as
Adjust CHx Result by
Read ADRx after SCF is set
difference between
result and 8 LSB
calculated offset
Sample CH15
Sample CHx
CH15=1 + CHx = 1
ADC
clock limits.
CH15 is a trimmed
reference of 8 LSB
(requires CTRx)
Analog Digital Converter - ADC
MM912F634
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