mm912f634 Freescale Semiconductor, Inc, mm912f634 Datasheet - Page 114

• Manufacturer Part Number: mm912f634
• Description: Mm912f634 - Integrated S12 Based Relay Driver With Lin
• Manufacturer: Freescale Semiconductor, Inc

Table 136. SCI Control Register 3 (SCIC3)
Note:
Functional Description and Application Information
When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold by one bit time. Under
the worst case timing conditions allowed in LIN, it is possible that a 0x00 data character can appear to be 10.26 bit times long at
a slave which is running 14% faster than the master. This would trigger normal break detection circuitry which is designed to
detect a 10 bit break symbol. When the LBKDE bit is set, framing errors are inhibited and the break detection threshold changes
from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol.
4.15.2.6
Table 137. SCIC3 Field Descriptions
Freescale Semiconductor
Note:
Offset
96.
Reset
97.
TXINV
W
R
TXDIR
Field
ORIE
NEIE
FEIE
PEIE
R8
T8
(96)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
7
6
5
4
3
2
1
0
Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
(97)
0x46
Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data
bit to the left of the MSB of the buffered data in the SCID register. When reading 9-bit data, read R8 before reading SCID
because reading SCID completes automatic flag clearing sequences which could allow R8 and SCID to be overwritten with new
data.
Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit
data bit to the left of the MSB of the data in the SCID register. When writing 9-bit data, the entire 9-bit value is transferred to the
SCI shift register after SCID is written so T8 should be written (if it needs to change from its previous value) before SCID is
written. If T8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not
be written each time SCID is written.
TxD Pin Direction in Single-wire Mode — When the SCI is configured for single-wire half-duplex operation
(LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin.
0 TxD pin is an input in single-wire mode.
1 TxD pin is an output in single-wire mode.
Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.
0 Transmit data not inverted
1 Transmit data inverted
Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled (use polling).
1 Hardware interrupt requested when OR = 1.
Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled (use polling).
1 Hardware interrupt requested when NF = 1.
Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.
Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
R8
SCI Control Register 3 (SCIC3)
7
0
T8
6
0
TXDIR
0
5
TXINV
0
4
(94)
Description
ORIE
0
3
Serial Communication Interface (S08SCIV4)
NEIE
0
2
FEIE
1
0
Access: User read/write
MM912F634
PEIE
0
0
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