mm912f634 Freescale Semiconductor, Inc, mm912f634 Datasheet - Page 72

• Manufacturer Part Number: mm912f634
• Description: Mm912f634 - Integrated S12 Based Relay Driver With Lin
• Manufacturer: Freescale Semiconductor, Inc

Functional Description and Application Information
4.8
To wake-up the MM912F634 analog die from Stop or Sleep mode, several wake-up sources are implemented. As described in
Section 4.3, “Modes of
transition to Normal mode. A wake-up from Sleep mode will result in a transition to Reset mode. In any case, the source of the
wake-up can be identified by reading the Wake-up Source Register (WSR). The Wake-up Source Register (WSR) has to be read
after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (f
between the WSR read and MCR write.
In general, there are the following seven main wake-up sources:
4.8.1
4.8.1.1
Any state digital change on a Wake-up Enabled Lx input will issue a wake-up. In order to select and activate a Wake-up Input
(Lx), the Wake-up Control Register (WCR) must be configured with appropriate LxWE inputs enabled or disabled before entering
low power mode. The Lx - Wake-up may be combined with the Forced Wake-up.
Note: Selecting a Lx Input for wake-up will disable a selected analog input once entering low power mode.
Freescale Semiconductor
•
•
•
•
•
•
•
Wake-up by a state change of one of the Lx inputs
Wake-up by a state change of one of the Lx inputs during a cyclic sense
Wake-up due to a forced wake-up
Wake-up by the LIN module
Wake-up by D2D interface (Stop mode only)
Wake-up due to internal / external Reset (Stop mode only)
Wake-up due to loss of supply voltage (Sleep mode only)
Wake-up / Cyclic Sense
Wake-up Sources
Lx - Wake-up (Cyclic Sense Disabled)
D2DCLK
D2DINT
D2D3
D2D2
D2D1
D2D0
Operation", a wake-up from Stop mode will result in an interrupt (D2DINT) to the MCU combined with a
Wake Up
D2D
Wake Up
Module
Figure 20. Wake-up Sources
Wake Up
Forced
LIN Wake Up
Lx – Wake Up
Cyclic Wake Up
Cyclic Sense / Forced
Wake Up Timer
HS1
HS2
LIN
L0
L1
L2
L3
L4
L5
BASE
Wake-up / Cyclic Sense
LIN Bus
V
) delay are required
SUP
MM912F634
72