mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 85

• Manufacturer Part Number: mc9s12q128
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

2.3.2.2.3
Read: Anytime.
Write: Anytime.
Freescale Semiconductor
Module Base + 0x000A
DDRS[3:0]
Reset
Field
3–0
W
R
Direction Register Port S — This register configures each port S pin as either input or output.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is
forced to be an output if the SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel
is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTS
0
0
7
Port S Data Direction Register (DDRS)
or PTIS registers, when changing the DDRS register.
= Unimplemented or Reserved
0
0
6
Figure 2-12. Port S Data Direction Register (DDRS)
Table 2-11. DDRS Field Descriptions
0
0
5
MC9S12Q128
Rev 1.09
0
0
4
Description
Chapter 2 Port Integration Module (PIM9C32) Block Description
DDRS3
0
3
DDRS2
0
2
DDRS1
0
1
DDRS0
0
0
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