mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 298

• Manufacturer Part Number: mc9s12q128
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
10.3.2.4
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).
298
Module Base + 0x0003
TSEG2[2:0]
TSEG1[3:0]
SAMP
Field
6:4
3:0
7
Reset:
W
R
Sampling — This bit determines the number of CAN bus samples taken per bit time.
0 One sample per bit.
1 Three samples per bit
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
Table
Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
Table
MSCAN Bus Timing Register 1 (CANBTR1)
SAMP
1. This setting is not valid. Please refer to
0
7
10-7.
10-8.
TSEG22
0
0
1
1
:
Figure 10-7. MSCAN Bus Timing Register 1 (CANBTR1)
TSEG22
Table 10-6. CANBTR1 Register Field Descriptions
6
0
(1)
Figure
Figure
.
TSEG21
Table 10-7. Time Segment 2 Values
TSEG21
0
0
1
1
:
10-43). Time segment 2 (TSEG2) values are programmable as shown in
10-43). Time segment 1 (TSEG1) values are programmable as shown in
0
5
MC9S12Q128
Rev 1.09
TSEG20
TSEG20
Table 10-34
4
0
0
1
0
1
:
Description
TSEG13
for valid settings.
0
3
1 Tq clock cycle
Time Segment 2
2 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
TSEG12
:
2
0
(1)
TSEG11
Freescale Semiconductor
0
1
TSEG10
0
0