mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 380

• Manufacturer Part Number: mc9s12q128
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 13 Serial Communications Interface (S12SCIV2) Block Description
13.1.3
The SCI operation is the same independent of device resource mapping and bus interface mode. Different
power modes are available to facilitate power saving.
13.1.3.1
Normal mode of operation.
13.1.3.2
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1
(SCICR1).
13.1.3.3
The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not
affect the SCI register states, but the SCI module clock will be disabled. The SCI operation resumes from
where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset
aborts any transmission or reception in progress and resets the SCI.
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— Transmission complete
— Receiver full
— Idle receiver input
— Receiver overrun
— Noise error
— Framing error
— Parity error
Receiver framing error detection
Hardware parity checking
1/16 bit-time noise detection
If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.
If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation
state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver
enable bit, RE, or the transmitter enable bit, TE.
If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The
transmission or reception resumes when either an internal or external interrupt brings the CPU out
of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and
resets the SCI.
Modes of Operation
Run Mode
Wait Mode
Stop Mode
MC9S12Q128
Rev 1.09
Freescale Semiconductor