mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 165

• Manufacturer Part Number: mc9s12q128
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 6
Background Debug Module (BDMV4) Block Description
6.1
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12
core platform.
A block diagram of the BDM is shown in
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
BDMV4 has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to show the clock rate and a handshake
signal to indicate when an operation is complete. The system is backwards compatible with older external
interfaces.
6.1.1
Freescale Semiconductor
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Single-wire communication with host development system
BDMV4 (and BDM2): Enhanced capability for allowing more flexibility in clock rates
BDMV4: SYNC command to determine communication rate
BDMV4: GO_UNTIL command
BDMV4: Hardware handshake protocol to increase the performance of the serial communication
Active out of reset in special single-chip mode
Introduction
Features
SYSTEM
HOST
BDMACT
ENBDM
ENTAG
TRACE
SDV
BKGD
16-BIT SHIFT REGISTER
INSTRUCTION DECODE
Figure 6-1. BDM Block Diagram
AND EXECUTION
STANDARD BDM
LOOKUP TABLE
FIRMWARE
Figure
MC9S12Q128
Rev 1.09
6-1.
CONTROL LOGIC
BUS INTERFACE
CLKSW
AND
ADDRESS
DATA
CLOCKS
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