lpc1778 NXP Semiconductors, lpc1778 Datasheet - Page 59

• Manufacturer Part Number: lpc1778
• Description: 32-bit Arm Cortex-m3 Microcontroller; Up To 512 Kb Flash And 96 Kb Sram; Usb Device/host/otg; Ethernet; Lcd; Emc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC178x_7x
Objective data sheet
7.25.1 Features
7.25 General purpose 32-bit timers/external event counters
7.26 Pulse Width Modulator (PWM)
The LPC178x/7x include four 32-bit timer/counters. The timer/counter is designed to
count cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts, generate timed DMA requests, or perform other actions at specified
timer values, based on four match registers. Each timer/counter also includes two capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
The LPC178x/7x contain two PWMs. The PWM is based on the standard Timer block and
inherits all of its features, although only the PWM function is pinned out on the
LPC178x/7x. The Timer is designed to count cycles of the system derived clock and
optionally switch pins, generate interrupts or perform other actions when specified timer
values occur, based on seven match registers. The PWM function is in addition to these
features, and is based on match register events.
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Data rates to 1 Mbit/s on each bus.
32-bit register and RAM access.
Compatible with CAN specification 2.0B, ISO 11898-1.
Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN
buses.
Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
FullCAN messages can generate interrupts.
A 32-bit timer/counter with a programmable 32-bit prescaler.
Counter or timer operation.
Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
Up to two match registers can be used to generate timed DMA requests.
All information provided in this document is subject to legal disclaimers.
Rev. 00.04 — 8 July 2010
32-bit ARM Cortex-M3 microcontroller
LPC178x/7x
© NXP B.V. 2010. All rights reserved.
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