lpc1778 NXP Semiconductors, lpc1778 Datasheet - Page 2

• Manufacturer Part Number: lpc1778
• Description: 32-bit Arm Cortex-m3 Microcontroller; Up To 512 Kb Flash And 96 Kb Sram; Usb Device/host/otg; Ethernet; Lcd; Emc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC178x_7x
Objective data sheet
Memory:
LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistors (TFT) displays.
External Memory Controller (EMC) provides support for asynchronous static memory
devices such as RAM, ROM and flash, as well as dynamic memories such as single
data rate SDRAM.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, GPIO, and for
memory-to-memory transfers.
Serial interfaces:
Cortex-M3 system tick timer, including an external clock input option.
Standard JTAG test/debug interface as well as Serial Wire Debug and Serial
WireTrace Port options.
Emulation trace module supports real-time trace.
Boundary scan for simplified board testing.
Non-maskable Interrupt (NMI) input.
512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced
flash memory accelerator and location of the flash memory on the CPU local
code/data bus provides high code performance from flash.
96 kB on-chip SRAM includes:
64 kB of SRAM on the CPU with local code/data bus for high-performance CPU
access.
Two 16 kB SRAM blocks with separate access paths for higher throughput. These
SRAM blocks may be used for DMA memory as well as for general purpose
instruction and data storage.
4 kB on-chip EEPROM.
Dedicated DMA controller.
Selectable display resolution (up to 1024 × 768 pixels).
Supports up to 24-bit true-color mode.
Ethernet MAC with MII/RMII interface and associated DMA controller. These
functions reside on an independent AHB.
USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and
associated DMA controller.
Five UARTs with fractional baud rate generation, internal FIFOs, IrDA, DMA
support, and RS-485/EIA-485 support. One UART has full modem control I/O.
Three SSP controllers with FIFO and multi-protocol capabilities. The SSP
interfaces can be used with the GPDMA controller.
Three enhanced I2C-bus interfaces, one with a true open-drain output supporting
the full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two
with standard port pins. Enhancements include multiple address recognition and
monitor mode.
I
the GPDMA.
CAN controller with two channels.
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
All information provided in this document is subject to legal disclaimers.
Rev. 00.04 — 8 July 2010
32-bit ARM Cortex-M3 microcontroller
LPC178x/7x
© NXP B.V. 2010. All rights reserved.
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