lpc1778 NXP Semiconductors, lpc1778 Datasheet - Page 57

• Manufacturer Part Number: lpc1778
• Description: 32-bit Arm Cortex-m3 Microcontroller; Up To 512 Kb Flash And 96 Kb Sram; Usb Device/host/otg; Ethernet; Lcd; Emc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC178x_7x
Objective data sheet
7.21.1 Features
7.22.1 Features
7.21 SSP serial I/O controller
7.22 I
The LPC178x/7x contain three SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
The LPC178x/7x contain three I
The I
(SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
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C-bus serial I/O controllers
Maximum SSP speed of <tbd> Mbit/s (master) or <tbd> Mbit/s (slave)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supported by GPDMA
All I
(Fast I
up to 400 kbit/s.
The I
using pins P5[2] and P5[3].
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
2
C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
2
C-bus controllers can use standard GPIO pins with bit rates of up to 400 kbit/s
2
C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s for I2C0
2
C-bus). The I
All information provided in this document is subject to legal disclaimers.
Rev. 00.04 — 8 July 2010
2
C0-bus interface uses special open-drain pins with bit rates of
2
C-bus controllers.
32-bit ARM Cortex-M3 microcontroller
2
C is a multi-master bus and can be
LPC178x/7x
© NXP B.V. 2010. All rights reserved.
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