at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 98

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

12.8.4
12.8.5
98
AT90PWM81
Timer/Counter1 Interrupt Mask Register – TIMSK1
Timer/Counter1 Interrupt Flag Register – TIFR1
Register (TEMP). This temporary register is shared by all the other 16-bit registers.
Registers” on page 86.
• Bit 7, 6 – Res: Reserved Bits
These bits are unused bits in the AT90PWM81, and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see XXXX) is
executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 4, 3, 2,1 – Res: Reserved Bits
These bits are unused bits in the AT90PWM81, and will always read as zero.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (see
61) is executed when the TOV1 Flag, located in TIFR1, is set.
• Bit 7, 6 – Res: Reserved Bits
These bits are unused bits in the AT90PWM81, and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is
set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP
value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1
can be cleared by writing a logic one to its bit location.
• Bit 4, 3, 2,1 – Res: Reserved Bits
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WG.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alterna-
tively, TOV1 can be cleared by writing a logic one to its bit location.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R
7
–
0
7
–
R
0
6
–
R
0
6
–
R
0
5
ICIE1
R/W
0
R/W
5
ICF1
0
4
–
R
0
4
–
R
0
3
–
R
0
3
–
R
0
R/W
2
–
0
2
–
R/W
0
1
–
R/W
0
1
–
R/W
0
See “Accessing 16-bit
0
TOIE1
R/W
0
0
TOV1
R/W
0
Table 9-1 on page
7734M–AVR–03/10
TIFR1
TIMSK1