at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 68

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

10.2.2
10.2.3
10.2.4
68
AT90PWM81
Toggling the Pin
Switching Between Input and Output
Reading the Pin Value
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high
(one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven
low (zero).
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that
the SBI instruction can be used to toggle one single bit in a port.
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} =
0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn,
PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant
environment will not notice the difference between a strong high driver and a pull-up. If this is not the
case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user must use
either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an
intermediate step.
Table 10-1
Table 10-1.
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Regis-
ter bit. As shown in
This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock,
but it also introduces a delay.
externally applied pin value. The maximum and minimum propagation delays are denoted t
t
pd,min
DDxn
0
0
0
1
1
respectively.
summarizes the control signals for the pin value.
PORTxn
0
1
1
0
1
Port Pin Configurations
Figure
(in MCUCR)
10-2, the PINxn Register bit and the preceding latch constitute a synchronizer.
PUD
Figure 10-3
X
X
X
0
1
shows a timing diagram of the synchronization when reading an
Output
Output
Input
Input
Input
I/O
Pull-up
Yes
No
No
No
No
Comment
Default configuration after Reset.
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
7734M–AVR–03/10
pd,max
and