at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 82

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

11. External Interrupts
11.0.1
82
AT90PWM81
External Interrupt Control Register A – EICRA
The External Interrupts are triggered by the INT2:0 pins. Observe that, if enabled, the interrupts will trig-
ger even if the INT2:0 pins are configured as outputs. This feature provides a way of generating a software
interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up
as indicated in the specification for the External Interrupt Control Registers – EICRA (INT2:0). When the
external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the
pin is held low. Note that recognition of falling or rising edge interrupts on INT2:0 requires the presence
of an I/O clock, described in
all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level
must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The
changed level is sampled twice by the Watchdog Oscillator clock. The period of the Watchdog Oscillator
is 1 µs (nominal) at 5.0V and 25⋅C. The frequency of the Watchdog Oscillator is voltage dependent as
shown in the
required level during this sampling or if it is held until the end of the start-up time. The start-up time is
defined by the SUT fuses as described in
sampled twice by the Watchdog Oscillator clock but disappears before the end of the start-up time, the
MCU will still wake up, but no interrupt will be generated. The required level must be held long enough
for the MCU to complete the wake up to trigger the level interrupt.
• Bits 7..0 – ISC21, ISC20 – ISC01, ISC00: External Interrupt 2 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT2:0 if the SREG I-flag and the corre-
sponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the
interrupts are defined in
INT2:0 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last lon-
ger than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an
interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider
is enabled. If low level interrupt is selected, the low level must be held until the completion of the cur-
rently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an
interrupt request as long as the pin is held low.
Table 11-1.
Bit
Read/Write
Initial Value
ISCn1
0
0
1
1
ISCn0
“Electrical Characteristics(1)” on page
0
1
0
1
7
-
R
0
Interrupt Sense Control
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request
The falling edge between two samples of INTn generates an interrupt request.
The rising edge between two samples of INTn generates an interrupt request.
Table
6
-
R
0
“Clock Systems and their Distribution” on page
11-1. Edges on INT3..INT0 are registered asynchronously.The value on the
5
ISC21
R/W
0
(1)
“System Clock and Clock Options” on page
4
ISC20
R/W
0
3
ISC11
R/W
0
273. The MCU will wake up if the input has the
2
ISC10
R/W
0
1
ISC01
R/W
0
27. The I/O clock is halted in
0
ISC00
R/W
0
27. If the level is
7734M–AVR–03/10
EICRA