at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 188

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

15.5.3
188
AT90PWM81
SPI Data Register – SPDR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set
and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this
will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt han-
dling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set,
then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit
(and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing
the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM81 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Mas-
ter mode (see
When the SPI is configured as Slave, the SPI is only guaranteed to work at f
The SPI interface on the AT90PWM81 is also used for program memory and EEPROM downloading or
uploading. See
• Bits 7:0 - SPD7:0: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI
Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift
Register Receive buffer to be read.
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Table
7
SPD7
R/W
X
SPIF
R
0
Serial Programming Algorithm261
15-5). This means that the minimum SCK period will be two CPU clock periods.
6
SPD6
R/W
X
WCOL
R
0
5
SPD5
R/W
X
–
R
0
4
SPD4
R/W
X
–
R
0
for serial programming and verification.
3
SPD3
R/W
X
–
R
0
2
SPD2
R/W
X
–
R
0
1
SPD1
R/W
X
–
R
0
clkio
/4 or lower.
0
SPD0
R/W
X
SPI2X
R/W
0
7734M–AVR–03/10
SPDR
Undefined
SPSR