tza3017hw NXP Semiconductors, tza3017hw Datasheet - Page 17

• Manufacturer Part Number: tza3017hw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-rate Fibre Optic Transmitter
• Manufacturer: NXP Semiconductors

Philips Semiconductors
The termination mode is determined by pins MD0
and MD1; see Table 9.
Table 9 Input termination mode selection
The LVDS mode has a differential hysteresis of 30 mV
implemented by default. Setting bit PIHYST in I
register MUXCNF0 (address A2H) activates hysteresis for
all input modes.
Loop mode I/Os
In line loopback mode, the internal data and clock routing
switch selects serial data and clock signals from
inputs DIN, DINQ, CIN, and CINQ instead of from the
output of the multiplexer. Line loopback mode is activated
by a LOW level on pin ENLINQ. Line loopback mode is
also selected by setting bit ENLIN in I
MUXCNF2 (address A0H).
In diagnostic loopback mode, the synthesized serial data
and clock signals are available at loop mode output
pins DLOOP and DLOOPQ, and CLOOP and CLOOPQ
and at output pins DOUT and DOUTQ and COUT and
COUTQ. Diagnostic loopback mode is activated by
making pin ENLOUTQ LOW. Diagnostic loopback mode is
also selected by setting bit ENLOUT in I
register MUXCNF2 (address A0H).
Configuring the RF I/Os
The polarity of specific RF serial data and clock I/O signals
can be inverted using I
(address CBH) and IOCNF1 (address CAH).
To allow easier connection to other ICs, the pin
designations for input data can be exchanged with the pin
designations for input clock. The pin designations for
output data and output clock can also be exchanged.
The default pin designations for loop mode input data and
clock are exchanged by setting bit CDINSWAP in I
register IOCNF1 so that signals at pins CIN and CINQ are
treated as data and signals at pins DIN and DINQ are
treated as clock.
2003 May 14
PIN MD1
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
0
0
1
1
PIN MD0
0
1
0
1
2
C-bus registers IOCNF0
floating
LVDS
CML
LVPECL
INPUT
MODE
100
100
(hysteresis on)
50
50
2
C-bus register
TERMINATION
2
C-bus
to V
to V
differential
differential
CC
CC
2
C-bus
2
C-bus
2 V
17
The default pin designations for RF output data and clock
are exchanged by setting bit CDOUTSWAP in I
register IOCNF1 so that signals at pins COUT and
COUTQ are treated as data and signals at pins DOUT and
DOUTQ are treated as clock.
The default pin designations for Loop mode output data
and clock are exchanged by setting bit CDLOOPSWAP in
I
mode output data is present at pins CLOOP and CLOOPQ
and loop mode clock output is present at pins DLOOP and
DLOOPQ.
Outputs DOUT and DOUTQ and COUT and COUTQ can
be independently disabled by bits DOUTENA and
COUTENA in I
The amplitude of the RF serial output signals in CML drive
mode, is adjustable (in 16 steps) between 70 mV (p-p) and
1100 mV (p-p), single-ended, controlled by bits RFS in
I
amplitude is 280 mV (p-p), single-ended. The RF serial
outputs can be either DC or AC-coupled, terminated by
bit RFOUTTERM in I
(address CBH). The default termination is DC-coupled.
CMOS control inputs
CMOS control inputs UI, MUXR0, MUXR1, PAREVEN,
CLKDIR, ENLOUTQ, ENLINQ, MD0, MD1, FIFORESET
and CS(DR0) have an internal pull-up resistor so that
these pins go HIGH when open circuit, and only go LOW
when deliberately forced. This is also true for pins DR1
and DR2 in pre-programmed mode (pin UI is LOW).
In I
and SDA comply with the I
Power supply connections
Four separate supply domains (V
V
blocks. Each supply domain should be connected to a
common V
including the exposed die pad, must be connected.
The die pad connection to ground must have the lowest
possible inductance. Since the die pad is also used as the
main ground return of the chip, this connection must also
have a low DC impedance. The voltage supply levels
should be in accordance with the values specified in
Chapters “Characteristics” and “Limiting values”.
All external components should be surface mounted, with
a preferable size of 0603 or smaller. The components
must be mounted as close to the IC as possible.
2
2
C-bus register IOCNF0 (address CBH) so that loop
C-bus register IOCNF0 (address CBH). The default
CCA
2
C-bus control mode (pin UI is HIGH), pins SCL
) provide isolation between the various functional
CC
using a separate filter. All supply pins,
2
C-bus register IOCNF1 (address CAH).
2
C-bus register IOCNF0
2
C-bus interface standard.
DD
TZA3017HW
, V
Product specification
CCD
, V
CCO
2
C-bus
and