tza3017hw NXP Semiconductors, tza3017hw Datasheet - Page 12

• Manufacturer Part Number: tza3017hw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-rate Fibre Optic Transmitter
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Prescaler outputs
The frequency of prescaler outputs PRSCLO and
PRSCLOQ is the VCO frequency divided by a ratio of N.K.
If the synthesizer is in-lock, the frequency of the prescaler
output is equal to the reference frequency at CREF and
CREFQ divided by R. This provides an accurate reference
that can be used by other phase locked loops in the
application. If required, the polarity of the prescaler
outputs can be inverted by setting bit PRSCLOINV in
I
required, its output can be disabled by setting
bit PRSCLOEN to logic 0 in the same register. In addition,
the prescaler output can be set for type of output,
termination mode and signal amplitude. These parameter
settings also apply to the parallel clock outputs POCLK
and POCLKQ and parity error outputs PARERR and
PARERRQ. For programming details; see Section
“Configuring the parallel interface”.
Loss of Lock (LOL)
During normal operation, pin LOL should be LOW to
indicate that the clock synthesizer is in-lock and that the
output frequency corresponds to the programmed value.
If pin LOL goes HIGH, phase and/or frequency lock is lost,
and the output frequency may deviate from the
programmed value. The LOL function is also available
using I
Sections “Interrupt register” and “Status register”.
If bit LOL in register INTERRUPT is not masked, a loss of
lock condition will generate an interrupt signal at pin INT.
Bit LOL is masked by default; see Section “Interrupt
generation”.
Jitter performance
The clock synthesizer is optimized for minimum jitter
generation. For all SDH/SONET bit rates, the generated
jitter complies with ITU-T standard G.958 using a pure
reference clock. To ensure negligible loss of performance,
the reference signal should have a single sideband phase
noise of better than 140 dBc/Hz, at frequencies of more
than 12 kHz from the carrier. If reference divider R is used,
this negative value is allowed to increase at approximately
20
Reference input
For optimum jitter performance and Power Supply
Rejection Ratio (PSRR), the sensitive reference input
should be driven differentially. If the reference frequency
source (f
input should be terminated with an impedance which
2003 May 14
2
C-bus register IOCNF2. If no prescaler information is
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
log (R).
2
C-bus registers INTERRUPT and STATUS; see
ref
) is single-ended, the unused CREF or CREFQ
12
matches the source impedance R
The PSRR can be improved by AC coupling the reference
frequency source to inputs CREF and CREFQ. Any low
frequency noise injected from the f
attenuated by the resulting high-pass filter. The low cut-off
frequency of the AC coupling must be lower than the
reference frequency, otherwise the reference signal will be
attenuated and the signal to noise ratio will be made
worse. The value of coupling capacitor C is calculated
using the formula:
Multiplexer
The multiplexer comprises a high-speed input register, a
4-bit deep First In First Out (FIFO) elastic buffer, a parity
check circuit and a multiplexing tree.
Parallel data bus clocking schemes
The TZA3017HW supports both co-directional and
contra-directional clocking schemes for the parallel data
bus; see Figs 7 and 8. The clocking scheme is selected by
pin CLKDIR or I
MUXCNF1 (address A1H). Co-directional clocking is the
default setting, and is selected when pin CLKDIR is HIGH
or when I
With co-directional clocking selected, the incoming clock is
applied to pins PICLK and PICLKQ and the input data is
applied to pins D00 and D00Q to D15 and D15Q.
A parallel output clock is also available, if required, at
pins POCLK and POCLKQ, and can be disabled by
bit POCLKEN in I
handbook, halfpage
Fig.6
50
2
C-bus bit CLKDIR is set to logic 1.
Reference input with single-ended clock
source.
on-chip
2
50
C-bus bit CLKDIR in I
2
C-bus register MUXCNF1.
C
V CCD
C REF
C REFQ
off-chip
---------------------------------- -
2 R
source
1
C
C
f
source
ref
ref
TZA3017HW
R source
Product specification
power supply will be
2
; see Fig.6.
C-bus register
V CC
R source
f ref
MDB060