tza3017hw NXP Semiconductors, tza3017hw Datasheet - Page 16

• Manufacturer Part Number: tza3017hw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-rate Fibre Optic Transmitter
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Configuring the parallel interface
There are several options for configuring the parallel
interface which comprises the parallel data bus and
associated inputs and outputs. The options for parallel
clock outputs POCLK and POCLKQ, parity error outputs
PARERR and PARERRQ and prescaler outputs PRSCLO
and PRSCLOQ are: output driver type, termination mode
and output amplitude. I
bit MFOUTMODE selects either the CML or LVPECL
output driver. The default is LVPECL. Bit MFOUTTERM
sets the output termination mode to either standard
LVPECL or floating termination, or in CML mode, to either
DC or AC-coupled. In all cases, bits MFS adjust the
amplitude. The default output amplitude is 850 mV (p-p),
single-ended.
The signal polarity and selective enabling or disabling of
POCLK, POCLKQ, PRSCLO and PRSCLOQ can also be
configured. These options are set in I
registers MUXCNF1 (address A1H) and IOCNF2
(address C8H).
2003 May 14
handbook, full pagewidth
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
Floating and LVDS termination
V CCD
V EE
D
DQ
2
C-bus register IOCNF2,
50
50
Fig.10 Rail-to-rail input termination configurations.
2
C-bus
D
DQ
V CCD
V EE
CML termination
50
50
16
In I
bit PDINV inverts the polarity of the parallel data.
Setting bit PICLKINV inverts the co-directional input clock
on pins PICLK and PICLKQ so that the clock edge is
shifted by half a clock cycle, changing the rising edge to a
falling edge. This function can be used to resolve a parallel
data bus timing problem.
Rail-to-rail parallel data and clock inputs
The differential parallel data, parity and clock inputs,
D00 to D15, D00Q to D15Q, PARITY, PARITYQ, PICLK,
and PICLKQ can handle input swings from 100 mV,
single-ended, to a maximum of 1000 mV. These rail-to-rail
inputs can also accept any absolute value between V
and V
To keep the number of external components required to a
minimum, most of the common standards: LVPECL, CML
and LVDS are terminated internally; see Fig.10.
2
C-bus register MUXCNF2 (address A0H), setting
CC
.
D
DQ
V CCD
V EE
LVPECL termination
50
50
TZA3017HW
Product specification
MDB062
2 V
EE