tza3017hw NXP Semiconductors, tza3017hw Datasheet - Page 14

• Manufacturer Part Number: tza3017hw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-rate Fibre Optic Transmitter
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FIFO
In the co-directional clocking scheme, the FIFO input
register samples the incoming parallel data on the rising
edge of the clock signal at pins PICLK and PICLKQ.
Data is retrieved from the FIFO by an internal clock,
derived from the multiplexing tree clock generator.
This provides a high tolerance to jitter, or clock skew,
at inputs on the parallel interface; the FIFO can
compensate for brief phase deviations, or clock skew,
of up to plus or minus 1 unit interval. Large phase
deviations will most likely cause the FIFO to either
overflow or underflow, and is indicated by bit OVERFLOW
in both I
Sections “Interrupt register” and “Status register”. A FIFO
overflow is also indicated by a HIGH level at
pin OVERFLOW. If bit OVERFLOW in
register INTERRUPT is not masked, a FIFO overflow or
underflow condition will generate an interrupt signal at
pin INT; see Section “Interrupt generation”.
The overflow interrupt exists until the FIFO is reset by a
HIGH level on pin FIFORESET or by setting
bits FIFORESET and I2CFIFORESET in I
MUXCNF0 (address A2H). FIFORESET also initializes the
FIFO. For optimum performance, the FIFO should be reset
2003 May 14
handbook, full pagewidth
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
2
C-bus registers INTERRUPT and STATUS; see
FRAMER
TX_CLK_SRC
TX_PARITY
TX_DATA
2
Fig.8 Contra-directional clocking.
C-bus register
14
whenever there has been a Loss Of Lock condition, or
whenever the bit rate is changed.
The FIFORESET signal is re-timed by the internal clock
generator signal. The FIFO will initialize two clock cycles
after FIFORESET goes HIGH and is operational two clock
cycles after FIFORESET goes LOW. The FIFO can be
initialized automatically when an overflow occurs by
connecting pin OVERFLOW to pin FIFORESET.
Adjustable multiplexing ratio
For optimum layout connectivity, the physical positions of
parallel data bus pins D00 and D00Q to D15 and D15Q on
the chip are located either side of pin V
The number of parallel data bus inputs that are used
depends on the multiplexing ratio selected by pins MUXR0
and MUXR1 or by bits MUXR in I
register MUXCNF1 (address A1H). Any unused parallel
data bus inputs are disabled. The configuration settings
and active inputs for each multiplexing ratio are shown in
Table 8.
In I
is 16:1. For multiplexing ratios 16:1, 8:1 and 4:1, the MSB
is transmitted first. For multiplexing ratio 10:1, the LSB is
transmitted first.
16
16
2
C-bus control mode, the default multiplexing ratio
PARITY
PARITYQ
D00 to D15
D00Q to D15Q
POCLK
POCLKQ
FIFORESET CREF
TZA3017HW
system
clock
MGW566
2
C-bus
TZA3017HW
Product specification
EE
(pin 13).