hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 98

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 52
Parameter
Active bank A to Active bank B command period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-Precharge
Write recovery time for write with Auto-Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read command (slow
exit, lower power)
Exit precharge power-down to any valid command (other
than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
4) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
7) For each of the terms, if not already an integer, round to the next highest integer.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
12) MIN (
13) The
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
15) 0 ≤
16) 85 °C <
Data Sheet
V
powered down and then restarted through the specified initialization sequence before normal operation can continue.
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3 of this data
sheet.
recognized as low.
WR refers to the WR parameter stored in the MR.
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
output Slew Rate mis-match between DQS/DQS and associated DQ in any given cycle.
this value can be greater than the minimum specification limits for
no longer driving (
as valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
between 85 °C and 95 °C.
DDQ
T
t
CASE
HZ
t
= 1.8 V ± 0.1 V;
CL
,
,
T
t
RPST
t
CASE
≤ 85 °C
CH
Timing Parameter by Speed Grade - DDR2-667
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
and
≤ 95 °C
t
t
HZ
LZ
,
,
V
t
t
RPRE
RPST
DD
= 1.8 V ± 0.1 V. See notes
), or begins driving (
parameters are referenced to a specific voltage level, which specify when the device output is
V
REF
V
stabilizes. During the period before
TT
t
. See Chapter 8 for the reference load for timing measurements.
LZ
,
t
RPRE
3)4)5)6)
).
99
t
HZ
Symbol
t
t
t
t
t
WR
t
t
t
t
t
t
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
and
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
t
t
LZ
CL
transitions occur in the same access time windows
and
t
CH
DDR2-667
Min.
7.5
10
7.5
0.35
0.40
15
t
7.5
2
7 – AL
2
t
200
WR
RFC
).
/
t
+10
CK
V
t
CK
REF
refers to the application clock period.
stabilizes, CKE = 0.2 x
512-Mbit DDR2 SDRAM
Electrical Characteristics
Max.
—
—
—
—
0.60
—
—
—
—
—
—
—
09112003-SDM9-IQ3P
Rev. 1.6, 2005-08
Unit
ns
ns
ns
t
t
ns
t
ns
t
t
t
ns
t
CK
CK
CK
CK
CK
CK
CK
V
Notes
1)2)3)4)5)6)
17)18)
19)
20)
21)
22)
22)
DDQ
is